mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-08-01 11:16:06 -04:00
Make initial public release
This commit is contained in:
Joachim Strömbergson
Daniel Lublin
commit
715de60f4a
251 changed files with 881225 additions and 0 deletions
7
hw/application_fpga/core/uds/README.txt
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7
hw/application_fpga/core/uds/README.txt
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# uds
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Unique Device Secret core
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## Introduction
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This core store and protect the Unique Device Secret. The
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storage is implemented in discrete registers. The contents can be read once between chip reset, and only if the system is in not in application access mode.
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129
hw/application_fpga/core/uds/rtl/uds.v
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129
hw/application_fpga/core/uds/rtl/uds.v
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//======================================================================
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//
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// uds.v
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// --------
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// Top level wrapper for the uds core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module uds(
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input wire clk,
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input wire reset_n,
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output wire fw_app_mode,
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input wire cs,
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input wire [7 : 0] address,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_UDS_FIRST = 8'h10;
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localparam ADDR_UDS_LAST = 8'h17;
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localparam CORE_NAME0 = 32'h7564735f; // "uds_"
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localparam CORE_NAME1 = 32'h6d656d20; // "mem "
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localparam CORE_VERSION = 32'h00000001;
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg [31 : 0] uds_reg [0 : 7];
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initial $readmemh(`UDS_HEX, uds_reg);
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reg uds_rd_reg [0 : 7];
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reg uds_rd_we;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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reg [31 : 0] tmp_read_data;
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reg tmp_ready;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = tmp_ready;
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @ (posedge clk)
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begin : reg_update
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integer i;
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if (!reset_n) begin
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for (i = 0 ; i < 8 ; i = i + 1) begin
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uds_rd_reg[i] <= 1'h0;;
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end
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end
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else begin
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if (uds_rd_we) begin
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uds_rd_reg[address[2 : 0]] <= 1'h1;
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end
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end
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end // reg_update
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//----------------------------------------------------------------
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// api
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//
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// The interface command decoding logic.
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//----------------------------------------------------------------
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always @*
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begin : api
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uds_rd_we = 1'h0;
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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if (cs) begin
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tmp_ready = 1'h1;
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if (address == ADDR_NAME0) begin
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tmp_read_data = CORE_NAME0;
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end
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if (address == ADDR_NAME1) begin
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tmp_read_data = CORE_NAME1;
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end
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if (address == ADDR_VERSION) begin
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tmp_read_data = CORE_VERSION;
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end
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if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
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if (!fw_app_mode) begin
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if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
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tmp_read_data = uds_reg[address[2 : 0]];
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uds_rd_we = 1'h1;
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end
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end
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end
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end
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end
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endmodule // uds
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//======================================================================
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// EOF uds.v
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//======================================================================
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300
hw/application_fpga/core/uds/tb/tb_uds.v
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300
hw/application_fpga/core/uds/tb/tb_uds.v
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//======================================================================
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//
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// tb_uds.v
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// -----------
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// Testbench for the UDS core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module tb_uds();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 1;
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parameter DUMP_WAIT = 0;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_UDS_FIRST = 8'h10;
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localparam ADDR_UDS_LAST = 8'h17;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_cs;
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reg [7 : 0] tb_address;
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wire [31 : 0] tb_read_data;
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reg [31 : 0] read_data;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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uds dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.cs(tb_cs),
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.address(tb_address),
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.read_data(tb_read_data)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (tb_monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin : dump_dut_state
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integer i;
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$display("State of DUT");
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$display("------------");
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$display("Cycle: %08d", cycle_ctr);
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for (i = 0 ; i < 8 ; i = i + 1) begin
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$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x",
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i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
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end
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$display("");
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("--- All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("--- %02d tests completed - %02d test cases did not complete successfully.",
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tc_ctr, error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_monitor = 0;
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tb_clk = 1'h0;
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tb_reset_n = 1'h1;
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tb_cs = 1'h0;
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tb_address = 8'h0;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// read_word()
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//
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// Read a data word from the given address in the DUT.
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// the word read will be available in the global variable
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// read_data.
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//----------------------------------------------------------------
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task read_word(input [11 : 0] address);
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begin
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tb_address = address;
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tb_cs = 1;
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#(CLK_PERIOD);
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read_data = tb_read_data;
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tb_cs = 0;
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if (DEBUG)
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begin
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$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
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$display("");
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end
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end
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endtask // read_word
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//----------------------------------------------------------------
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// test1()
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//----------------------------------------------------------------
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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tb_monitor = 1'h0;
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$display("");
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$display("--- test1: started.");
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$display("--- test1: Reading NAME and version info.");
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read_word(ADDR_NAME0);
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read_word(ADDR_NAME1);
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read_word(ADDR_VERSION);
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$display("--- test1: Dumping DUT state to show UDS contents");
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dump_dut_state();
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$display("--- test1: Reading UDS words.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading rest of the words.");
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading UDS words again.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: Resetting DUT.");
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reset_dut();
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$display("--- test1: Dumping state again to see read bits.");
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dump_dut_state();
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$display("--- test1: Reading UDS words.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: Reading UDS words again.");
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read_word(ADDR_UDS_FIRST + 0);
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read_word(ADDR_UDS_FIRST + 1);
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read_word(ADDR_UDS_FIRST + 2);
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read_word(ADDR_UDS_FIRST + 3);
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read_word(ADDR_UDS_FIRST + 4);
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read_word(ADDR_UDS_FIRST + 5);
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read_word(ADDR_UDS_FIRST + 6);
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read_word(ADDR_UDS_FIRST + 7);
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$display("--- test1: completed.");
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$display("");
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end
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endtask // tes1
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//----------------------------------------------------------------
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// uds_test
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//----------------------------------------------------------------
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initial
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begin : uds_test
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$display("");
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$display(" -= Testbench for uds started =-");
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$display(" ===========================");
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$display("");
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init_sim();
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reset_dut();
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test1();
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display_test_result();
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$display("");
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$display(" -= Testbench for uds started =-");
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$display(" ===========================");
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$display("");
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$finish;
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end // uds_test
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endmodule // tb_uds
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//======================================================================
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// EOF tb_uds.v
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//======================================================================
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55
hw/application_fpga/core/uds/toolruns/Makefile
Executable file
55
hw/application_fpga/core/uds/toolruns/Makefile
Executable file
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@ -0,0 +1,55 @@
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#===================================================================
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#
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# Makefile
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# --------
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# Makefile for building the UDS core.
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#
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#
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# Author: Joachim Strombergson
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# Copyright (C) 2022 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#===================================================================
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TOP_SRC=../rtl/uds.v
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TB_TOP_SRC =../tb/tb_uds.v
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CC = iverilog
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CC_FLAGS = -Wall
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LINT = verilator
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LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
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all: top.sim
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top.sim: $(TB_TOP_SRC) $(TOP_SRC)
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$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC)
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sim-top: top.sim
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./top.sim
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lint-top: $(TOP_SRC)
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$(LINT) $(LINT_FLAGS) $(TOP_SRC)
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clean:
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rm -f top.sim
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help:
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@echo "Build system for simulation of UDS core"
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@echo ""
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@echo "Supported targets:"
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@echo "------------------"
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@echo "top.sim: Build top level simulation target."
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@echo "sim-top: Run top level simulation."
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@echo "lint-top: Lint top rtl source files."
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@echo "clean: Delete all built files."
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#===================================================================
|
||||
# EOF Makefile
|
||||
#===================================================================
|
||||
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