130 lines
3.4 KiB
Verilog
130 lines
3.4 KiB
Verilog
//======================================================================
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//
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// uds.v
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// --------
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// Top level wrapper for the uds core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module uds(
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input wire clk,
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input wire reset_n,
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output wire fw_app_mode,
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input wire cs,
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input wire [7 : 0] address,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_UDS_FIRST = 8'h10;
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localparam ADDR_UDS_LAST = 8'h17;
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localparam CORE_NAME0 = 32'h7564735f; // "uds_"
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localparam CORE_NAME1 = 32'h6d656d20; // "mem "
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localparam CORE_VERSION = 32'h00000001;
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg [31 : 0] uds_reg [0 : 7];
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initial $readmemh(`UDS_HEX, uds_reg);
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reg uds_rd_reg [0 : 7];
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reg uds_rd_we;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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reg [31 : 0] tmp_read_data;
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reg tmp_ready;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = tmp_ready;
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @ (posedge clk)
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begin : reg_update
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integer i;
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if (!reset_n) begin
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for (i = 0 ; i < 8 ; i = i + 1) begin
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uds_rd_reg[i] <= 1'h0;;
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end
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end
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else begin
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if (uds_rd_we) begin
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uds_rd_reg[address[2 : 0]] <= 1'h1;
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end
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end
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end // reg_update
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//----------------------------------------------------------------
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// api
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//
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// The interface command decoding logic.
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//----------------------------------------------------------------
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always @*
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begin : api
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uds_rd_we = 1'h0;
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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if (cs) begin
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tmp_ready = 1'h1;
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if (address == ADDR_NAME0) begin
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tmp_read_data = CORE_NAME0;
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end
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if (address == ADDR_NAME1) begin
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tmp_read_data = CORE_NAME1;
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end
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if (address == ADDR_VERSION) begin
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tmp_read_data = CORE_VERSION;
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end
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if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
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if (!fw_app_mode) begin
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if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
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tmp_read_data = uds_reg[address[2 : 0]];
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uds_rd_we = 1'h1;
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end
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end
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end
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end
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end
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endmodule // uds
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//======================================================================
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// EOF uds.v
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//======================================================================
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