From 6d8c0aff6492f25b6fd149fc321f7044b86cfbb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 15 Aug 2024 12:43:30 +0200 Subject: [PATCH] (fpga) Update README with info on the free running mode. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim StroĢˆmbergson --- hw/application_fpga/core/timer/README.md | 52 ++++++++++++------------ 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/hw/application_fpga/core/timer/README.md b/hw/application_fpga/core/timer/README.md index 826e75d..902dc9d 100644 --- a/hw/application_fpga/core/timer/README.md +++ b/hw/application_fpga/core/timer/README.md @@ -1,37 +1,39 @@ # timer -A simple timer with prescaler. +Timer with prescaler and support for free running mode. ## Introduction -This core implements a simple timer with a prescaler. The prescaler -allows measurement of time durations rather than cycles. If for -example setting the prescaler to the clock frequency in Hertz, the -timer will count seconds. +This core implements a simple timer with a prescaler and support for a +free running mode. + +The prescaler allows measurement of time durations rather than +cycles. If for example setting the prescaler to the clock frequency in +Hertz, the timer will count seconds. After (prescaler * timer) number +of cycles the timer will stop. Checking status of the timer can be +done by reading the STATUS_RUNNING_BIT. If set to zero, the timer has +completed. + +If the free running mode is set (default off), the counter will not +stup when the number of cycles defined by (prescaler * timer) has been +reached. Instead the timer continues until the CTRL_STOP_BIT is +asserted. Note that in free running mode, the ADDR_PRESCALER shall be +set to one (1). + ## API - The following addresses define the API for the timer: ``` - ADDR_CTRL: 0x08 - CTRL_START_BIT: 0 - CTRL_STOP_BIT: 1 + ADDR_CTRL: 0x08 + CTRL_START_BIT: 0 + CTRL_STOP_BIT: 1 - ADDR_STATUS: 0x09 + ADDR_STATUS: 0x09 STATUS_RUNNING_BIT: 0 - ADDR_PRESCALER: 0x0a - ADDR_TIMER: 0x0b + ADDR_PRESCALER: 0x0a + ADDR_TIMER: 0x0b + + ADDR_FREE_RUNNING: 0x0c + FREE_RUNNING_BIT 0 + ``` - - -## Details -The core consists of the timer_core module (in timer_core.v) and a top -level wrapper, timer (in timer.v). The top level wrapper implements -the API, while the timer_core implements the actual timer -functionality. - -The timer counter and the prescaler counter are both 32 bits. -When enabled the counter counts down one integer value per cycle. - -The timer will stop when reaching final zero (given by prescaler times the initial value of the timer) -and the running flag will be lowered.