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Raise bps to 62500

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Daniel Lublin 2022-10-19 15:32:55 +02:00
parent b8f1d4a083
commit 675fa1087f
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3 changed files with 15 additions and 6 deletions
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8
doc/release_notes.md
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@ -11,6 +11,14 @@ using firmware from this commit and onwards your CDI and with it the
private key of the signerapp will change even if you haven't changed private key of the signerapp will change even if you haven't changed
the app in any way. the app in any way.
### Change of serial port communication speed
For stability and speed considerations we're raising the speed used
for communication with the device over the serial port. The serial
port UART speed is raised from 38400 to 62500 bps (Bits Per Second).
Host programs in the tillitis-key1-apps repo are also adjusted
accordingly.
## engineering-release-1 ## engineering-release-1
### Hardware ### Hardware

7
hw/application_fpga/core/uart/rtl/uart.v
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@ -82,9 +82,10 @@ module uart(
// The default bit rate is based on target clock frequency // The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the // divided by the bit rate times in order to hit the
// center of the bits. I.e. // center of the bits. I.e.
// Clock: 18 MHz, 38400 bps // Clock: 18 MHz, 62500 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469 // Divisor = 18E6 / 62500 = 288
localparam DEFAULT_BIT_RATE = 16'd469; // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd288;
localparam DEFAULT_DATA_BITS = 4'h8; localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1; localparam DEFAULT_STOP_BITS = 2'h1;

6
hw/application_fpga/tb/application_fpga_verilator.cc
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@ -24,9 +24,9 @@
#include "Vapplication_fpga.h" #include "Vapplication_fpga.h"
#include "verilated.h" #include "verilated.h"
// Clock: 18 MHz, 38400 bps // Clock: 18 MHz, 62500 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469 // Divisor = 18E6 / 62500 = 288
#define BIT_DIV 469 #define BIT_DIV 288
struct uart { struct uart {
int bit_div; int bit_div;