diff --git a/doc/release_notes.md b/doc/release_notes.md
index 896c8c1..33b7989 100644
--- a/doc/release_notes.md
+++ b/doc/release_notes.md
@@ -11,6 +11,14 @@ using firmware from this commit and onwards your CDI and with it the
 private key of the signerapp will change even if you haven't changed
 the app in any way.
 
+### Change of serial port communication speed
+
+For stability and speed considerations we're raising the speed used
+for communication with the device over the serial port. The serial
+port UART speed is raised from 38400 to 62500 bps (Bits Per Second).
+Host programs in the tillitis-key1-apps repo are also adjusted
+accordingly.
+
 ## engineering-release-1
 
 ### Hardware
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
index d84d8ec..480ba37 100644
--- a/hw/application_fpga/core/uart/rtl/uart.v
+++ b/hw/application_fpga/core/uart/rtl/uart.v
@@ -82,9 +82,10 @@ module uart(
   // The default bit rate is based on target clock frequency
   // divided by the bit rate times in order to hit the
   // center of the bits. I.e.
-  // Clock: 18 MHz, 38400 bps
-  // Divisor = 18*10E6 / 38400 = 468.75 ~ 469
-  localparam DEFAULT_BIT_RATE  = 16'd469;
+  // Clock: 18 MHz, 62500 bps
+  // Divisor = 18E6 / 62500 = 288
+  // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
+  localparam DEFAULT_BIT_RATE  = 16'd288;
   localparam DEFAULT_DATA_BITS = 4'h8;
   localparam DEFAULT_STOP_BITS = 2'h1;
 
diff --git a/hw/application_fpga/tb/application_fpga_verilator.cc b/hw/application_fpga/tb/application_fpga_verilator.cc
index f7a4b33..29cd1be 100644
--- a/hw/application_fpga/tb/application_fpga_verilator.cc
+++ b/hw/application_fpga/tb/application_fpga_verilator.cc
@@ -24,9 +24,9 @@
 #include "Vapplication_fpga.h"
 #include "verilated.h"
 
-// Clock: 18 MHz, 38400 bps
-// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
-#define BIT_DIV 469
+// Clock: 18 MHz, 62500 bps
+// Divisor = 18E6 / 62500 = 288
+#define BIT_DIV 288
 
 struct uart {
 	int bit_div;