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Raise bps to 62500

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Daniel Lublin 2022-10-19 15:32:55 +02:00
parent b8f1d4a083
commit 675fa1087f
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3 changed files with 15 additions and 6 deletions
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6
hw/application_fpga/tb/application_fpga_verilator.cc
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@ -24,9 +24,9 @@
#include "Vapplication_fpga.h"
#include "verilated.h"
// Clock: 18 MHz, 38400 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
#define BIT_DIV 469
// Clock: 18 MHz, 62500 bps
// Divisor = 18E6 / 62500 = 288
#define BIT_DIV 288
struct uart {
int bit_div;