Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-09-21 21:34:39 -04:00
Code Issues Projects Releases Packages Wiki Activity

Raise bps to 62500

Browse source
This commit is contained in:
Daniel Lublin 2022-10-19 15:32:55 +02:00
parent b8f1d4a083
commit 675fa1087f
No known key found for this signature in database
GPG key ID: 75BD0FEB8D3E7830
3 changed files with 15 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

7
hw/application_fpga/core/uart/rtl/uart.v
View file

@ -82,9 +82,10 @@ module uart(
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 18 MHz, 38400 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
localparam DEFAULT_BIT_RATE = 16'd469;
// Clock: 18 MHz, 62500 bps
// Divisor = 18E6 / 62500 = 288
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd288;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;

6
hw/application_fpga/tb/application_fpga_verilator.cc
View file

@ -24,9 +24,9 @@
#include "Vapplication_fpga.h"
#include "verilated.h"
// Clock: 18 MHz, 38400 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
#define BIT_DIV 469
// Clock: 18 MHz, 62500 bps
// Divisor = 18E6 / 62500 = 288
#define BIT_DIV 288
struct uart {
int bit_div;