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Merge branch 'bigger_rx_fifo'

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This commit is contained in:
Joachim Strömbergson 2022-11-02 14:22:46 +01:00
commit 517fafff57
1 changed files with 37 additions and 18 deletions
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55
hw/application_fpga/core/uart/rtl/uart_fifo.v
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@ -3,6 +3,7 @@
// uart_fifo.v // uart_fifo.v
// ----------- // -----------
// FIFO for rx and tx data buffering in the UART. // FIFO for rx and tx data buffering in the UART.
// The code should allocate a single EBR in a iCE40UP device.
// //
// //
// Author: Joachim Strombergson // Author: Joachim Strombergson
@ -52,19 +53,19 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [7 : 0] fifo_mem [0 : 255]; reg [7 : 0] fifo_mem [0 : 511];
reg fifo_mem_we; reg fifo_mem_we;
reg [7: 0] in_ptr_reg; reg [8: 0] in_ptr_reg;
reg [7: 0] in_ptr_new; reg [8: 0] in_ptr_new;
reg in_ptr_we; reg in_ptr_we;
reg [7: 0] out_ptr_reg; reg [8: 0] out_ptr_reg;
reg [7: 0] out_ptr_new; reg [8: 0] out_ptr_new;
reg out_ptr_we; reg out_ptr_we;
reg [7: 0] byte_ctr_reg; reg [8: 0] byte_ctr_reg;
reg [7: 0] byte_ctr_new; reg [8: 0] byte_ctr_new;
reg byte_ctr_inc; reg byte_ctr_inc;
reg byte_ctr_dec; reg byte_ctr_dec;
reg byte_ctr_we; reg byte_ctr_we;
@ -73,12 +74,18 @@ module uart_fifo(
reg in_ack_new; reg in_ack_new;
//----------------------------------------------------------------
// Wires
//----------------------------------------------------------------
reg fifo_empty;
reg fifo_full;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Concurrent connectivity for ports etc. // Concurrent connectivity for ports etc.
//---------------------------------------------------------------- //----------------------------------------------------------------
assign in_ack = in_ack_reg; assign in_ack = in_ack_reg;
assign out_syn = ~fifo_empty;
assign out_syn = |byte_ctr_reg;
assign out_data = fifo_mem[out_ptr_reg]; assign out_data = fifo_mem[out_ptr_reg];
@ -88,9 +95,9 @@ module uart_fifo(
always @ (posedge clk) always @ (posedge clk)
begin: reg_update begin: reg_update
if (!reset_n) begin if (!reset_n) begin
in_ptr_reg <= 8'h0; in_ptr_reg <= 9'h0;
out_ptr_reg <= 8'h0; out_ptr_reg <= 9'h0;
byte_ctr_reg <= 8'h0; byte_ctr_reg <= 9'h0;
in_ack_reg <= 1'h0; in_ack_reg <= 1'h0;
end end
else begin else begin
@ -120,9 +127,19 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @*
begin : byte_ctr begin : byte_ctr
byte_ctr_new = 8'h0; fifo_empty = 1'h0;
fifo_full = 1'h0;
byte_ctr_new = 9'h0;
byte_ctr_we = 1'h0; byte_ctr_we = 1'h0;
if (byte_ctr_reg == 9'h0) begin
fifo_empty = 1'h1;
end
if (byte_ctr_reg == 9'h1ff) begin
fifo_full = 1'h1;
end
if ((byte_ctr_inc) && (!byte_ctr_dec)) begin if ((byte_ctr_inc) && (!byte_ctr_dec)) begin
byte_ctr_new = byte_ctr_reg + 1'h1; byte_ctr_new = byte_ctr_reg + 1'h1;
byte_ctr_we = 1'h1; byte_ctr_we = 1'h1;
@ -143,10 +160,11 @@ module uart_fifo(
fifo_mem_we = 1'h0; fifo_mem_we = 1'h0;
in_ack_new = 1'h0; in_ack_new = 1'h0;
byte_ctr_inc = 1'h0; byte_ctr_inc = 1'h0;
in_ptr_new = in_ptr_reg + 1'h1;
in_ptr_we = 1'h0; in_ptr_we = 1'h0;
if ((in_syn) && (!in_ack) && (byte_ctr_reg < 8'hff)) begin in_ptr_new = in_ptr_reg + 1'h1;
if ((in_syn) && (!in_ack) && (!fifo_full)) begin
fifo_mem_we = 1'h1; fifo_mem_we = 1'h1;
in_ack_new = 1'h1; in_ack_new = 1'h1;
byte_ctr_inc = 1'h1; byte_ctr_inc = 1'h1;
@ -161,10 +179,11 @@ module uart_fifo(
always @* always @*
begin : out_logic begin : out_logic
byte_ctr_dec = 1'h0; byte_ctr_dec = 1'h0;
out_ptr_new = out_ptr_reg + 1'h1;
out_ptr_we = 1'h0; out_ptr_we = 1'h0;
if ((out_ack) && (byte_ctr_reg > 8'h0)) begin out_ptr_new = out_ptr_reg + 1'h1;
if ((out_ack) && (!fifo_empty)) begin
byte_ctr_dec = 1'h1; byte_ctr_dec = 1'h1;
out_ptr_we = 1'h1; out_ptr_we = 1'h1;
end end