From 0eacbca2f9f75b7a591f44a362b2171949c8bc9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Fri, 28 Oct 2022 12:48:13 +0200 Subject: [PATCH 1/3] Increase size of RX-FIFO to 512 bytes --- hw/application_fpga/core/uart/rtl/uart_fifo.v | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v index 11fa3dd..9d07602 100644 --- a/hw/application_fpga/core/uart/rtl/uart_fifo.v +++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v @@ -52,19 +52,19 @@ module uart_fifo( //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- - reg [7 : 0] fifo_mem [0 : 255]; + reg [7 : 0] fifo_mem [0 : 511]; reg fifo_mem_we; - reg [7: 0] in_ptr_reg; - reg [7: 0] in_ptr_new; + reg [8: 0] in_ptr_reg; + reg [8: 0] in_ptr_new; reg in_ptr_we; - reg [7: 0] out_ptr_reg; - reg [7: 0] out_ptr_new; + reg [8: 0] out_ptr_reg; + reg [8: 0] out_ptr_new; reg out_ptr_we; - reg [7: 0] byte_ctr_reg; - reg [7: 0] byte_ctr_new; + reg [8: 0] byte_ctr_reg; + reg [8: 0] byte_ctr_new; reg byte_ctr_inc; reg byte_ctr_dec; reg byte_ctr_we; @@ -88,9 +88,9 @@ module uart_fifo( always @ (posedge clk) begin: reg_update if (!reset_n) begin - in_ptr_reg <= 8'h0; - out_ptr_reg <= 8'h0; - byte_ctr_reg <= 8'h0; + in_ptr_reg <= 9'h0; + out_ptr_reg <= 9'h0; + byte_ctr_reg <= 9'h0; in_ack_reg <= 1'h0; end else begin @@ -120,7 +120,7 @@ module uart_fifo( //---------------------------------------------------------------- always @* begin : byte_ctr - byte_ctr_new = 8'h0; + byte_ctr_new = 9'h0; byte_ctr_we = 1'h0; if ((byte_ctr_inc) && (!byte_ctr_dec)) begin @@ -146,7 +146,7 @@ module uart_fifo( in_ptr_new = in_ptr_reg + 1'h1; in_ptr_we = 1'h0; - if ((in_syn) && (!in_ack) && (byte_ctr_reg < 8'hff)) begin + if ((in_syn) && (!in_ack) && (byte_ctr_reg < 9'h1ff)) begin fifo_mem_we = 1'h1; in_ack_new = 1'h1; byte_ctr_inc = 1'h1; @@ -164,7 +164,7 @@ module uart_fifo( out_ptr_new = out_ptr_reg + 1'h1; out_ptr_we = 1'h0; - if ((out_ack) && (byte_ctr_reg > 8'h0)) begin + if ((out_ack) && (byte_ctr_reg > 9'h0)) begin byte_ctr_dec = 1'h1; out_ptr_we = 1'h1; end From 24d8680772de37a708100b6af1bdcad3d4d8b05c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Fri, 28 Oct 2022 13:09:21 +0200 Subject: [PATCH 2/3] Improve detection of empty and full FIFO --- hw/application_fpga/core/uart/rtl/uart_fifo.v | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v index 9d07602..950f03a 100644 --- a/hw/application_fpga/core/uart/rtl/uart_fifo.v +++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v @@ -3,6 +3,7 @@ // uart_fifo.v // ----------- // FIFO for rx and tx data buffering in the UART. +// The code should allocate a single EBR in a iCE40UP device. // // // Author: Joachim Strombergson @@ -73,6 +74,13 @@ module uart_fifo( reg in_ack_new; + //---------------------------------------------------------------- + // Wires + //---------------------------------------------------------------- + reg fifo_empty; + reg fifo_full; + + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- @@ -120,9 +128,19 @@ module uart_fifo( //---------------------------------------------------------------- always @* begin : byte_ctr + fifo_empty = 1'h0; + fifo_full = 1'h0; byte_ctr_new = 9'h0; byte_ctr_we = 1'h0; + if (byte_ctr_reg == 9'h0) begin + fifo_empty = 1'h1; + end + + if (byte_ctr_reg == 9'h1ff) begin + fifo_full = 1'h1; + end + if ((byte_ctr_inc) && (!byte_ctr_dec)) begin byte_ctr_new = byte_ctr_reg + 1'h1; byte_ctr_we = 1'h1; @@ -143,10 +161,11 @@ module uart_fifo( fifo_mem_we = 1'h0; in_ack_new = 1'h0; byte_ctr_inc = 1'h0; - in_ptr_new = in_ptr_reg + 1'h1; in_ptr_we = 1'h0; - if ((in_syn) && (!in_ack) && (byte_ctr_reg < 9'h1ff)) begin + in_ptr_new = in_ptr_reg + 1'h1; + + if ((in_syn) && (!in_ack) && (!fifo_full)) begin fifo_mem_we = 1'h1; in_ack_new = 1'h1; byte_ctr_inc = 1'h1; @@ -161,10 +180,11 @@ module uart_fifo( always @* begin : out_logic byte_ctr_dec = 1'h0; - out_ptr_new = out_ptr_reg + 1'h1; out_ptr_we = 1'h0; - if ((out_ack) && (byte_ctr_reg > 9'h0)) begin + out_ptr_new = out_ptr_reg + 1'h1; + + if ((out_ack) && (!fifo_empty)) begin byte_ctr_dec = 1'h1; out_ptr_we = 1'h1; end From 8061491f6e4af07b00782278a99c6d87cafceee9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Fri, 28 Oct 2022 13:12:47 +0200 Subject: [PATCH 3/3] Cleanup, and use fifo_empty to indicate data available --- hw/application_fpga/core/uart/rtl/uart_fifo.v | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v index 950f03a..e620bb0 100644 --- a/hw/application_fpga/core/uart/rtl/uart_fifo.v +++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v @@ -84,9 +84,8 @@ module uart_fifo( //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign in_ack = in_ack_reg; - - assign out_syn = |byte_ctr_reg; + assign in_ack = in_ack_reg; + assign out_syn = ~fifo_empty; assign out_data = fifo_mem[out_ptr_reg];