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FPGA: Ignore lint warnings in cell library

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For Verilator >5.019 `-Wno-GENUNNAMED` needs to be added to LINT_FLAGS
to silence warnings from the cell library.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-17 13:30:13 +02:00 committed by dehanj
parent bb4469ffda
commit 49e81be1e1
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1 changed files with 4 additions and 1 deletions
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5
hw/application_fpga/Makefile
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@ -186,7 +186,10 @@ check-binary-hashes:
# Source linting.
#-------------------------------------------------------------------
LINT=verilator
LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-DECLFILENAME \
# For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the
# cell library.
LINT_FLAGS = +1364-2005ext+ --lint-only \
-Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND \
--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)