From 49e81be1e16d50b949b5e01ee228bb92a3fd8b66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 17 Jun 2024 13:30:13 +0200 Subject: [PATCH] FPGA: Ignore lint warnings in cell library MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For Verilator >5.019 `-Wno-GENUNNAMED` needs to be added to LINT_FLAGS to silence warnings from the cell library. Signed-off-by: Joachim Strömbergson --- hw/application_fpga/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index a32203c..10f2570 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -186,7 +186,10 @@ check-binary-hashes: # Source linting. #------------------------------------------------------------------- LINT=verilator -LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-DECLFILENAME \ +# For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the +# cell library. +LINT_FLAGS = +1364-2005ext+ --lint-only \ + -Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND \ --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)