Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity

fpga: Add testcase for SPI access control

Browse Source 
Add testcase that checks that access control
      is enabled and disabled as expected.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-07-11 13:21:20 +02:00
parent 7e26c742bf
commit 4233777831
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
1 changed files with 74 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

104
hw/application_fpga/core/tk1/tb/tb_tk1.v
View File

@ -61,6 +61,7 @@ module tb_tk1();
localparam ADDR_SPI_EN = 8'h80; localparam ADDR_SPI_EN = 8'h80;
localparam ADDR_SPI_XFER = 8'h81; localparam ADDR_SPI_XFER = 8'h81;
localparam ADDR_SPI_DATA = 8'h82; localparam ADDR_SPI_DATA = 8'h82;
localparam ADDR_SPI_CMD = 8'h83;
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -130,9 +131,6 @@ module tb_tk1();
.cpu_valid(tb_cpu_valid), .cpu_valid(tb_cpu_valid),
.force_trap(tb_force_trap), .force_trap(tb_force_trap),
.ram_access(tb_ram_access),
.rom_access(tb_rom_access),
.ram_aslr(tb_ram_aslr), .ram_aslr(tb_ram_aslr),
.ram_scramble(tb_ram_scramble), .ram_scramble(tb_ram_scramble),
@ -272,9 +270,6 @@ module tb_tk1();
tb_cpu_valid = 1'h0; tb_cpu_valid = 1'h0;
tb_cpu_trap = 1'h0; tb_cpu_trap = 1'h0;
tb_ram_access = 1'h0;
tb_rom_access = 1'h0;
tb_gpio1 = 1'h0; tb_gpio1 = 1'h0;
tb_gpio2 = 1'h0; tb_gpio2 = 1'h0;
@ -296,8 +291,7 @@ module tb_tk1();
begin begin
if (DEBUG) if (DEBUG)
begin begin
$display("--- Writing 0x%08x to 0x%02x.", word, address); $display("--- Write word: 0x%08x to 0x%02x.", word, address);
$display("");
end end
tb_address = address; tb_address = address;
@ -334,13 +328,11 @@ module tb_tk1();
if (DEBUG) if (DEBUG)
begin begin
if (read_data == expected) begin if (read_data == expected) begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address); $display("--- Read word: 0x%08x from 0x%02x.", read_data, address);
end else begin end else begin
$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", $display("--- Read word: Error. Got 0x%08x, expected 0x%08x", read_data, address, expected);
read_data, address, expected);
error_ctr = error_ctr + 1; error_ctr = error_ctr + 1;
end end
$display("");
end end
end end
endtask // read_word endtask // read_word
@ -654,6 +646,13 @@ module tb_tk1();
begin begin
tc_ctr = tc_ctr + 1; tc_ctr = tc_ctr + 1;
// We need to enable SPI access before testing.
dut.spi_access_ctrl_new = 1'h1;
dut.spi_access_ctrl_we = 1'h1;
#(CLK_PERIOD);
dut.spi_access_ctrl_new = 1'h0;
dut.spi_access_ctrl_we = 1'h0;
$display(""); $display("");
$display("--- test10: Loopback in SPI Master started."); $display("--- test10: Loopback in SPI Master started.");
@ -668,8 +667,9 @@ module tb_tk1();
$display("--- test10: Byte should have been sent."); $display("--- test10: Byte should have been sent.");
write_word(ADDR_SPI_EN, 32'h0); write_word(ADDR_SPI_EN, 32'h0);
// 0x58 is the inverse of 0xa7. // Read back data. 0x58 is the inverse of 0xa7.
read_word(ADDR_SPI_DATA, 32'h58); read_word(ADDR_SPI_DATA, 32'h58);
write_word(ADDR_SPI_EN, 32'h0);
$display("--- test10: completed."); $display("--- test10: completed.");
$display(""); $display("");
@ -689,32 +689,76 @@ module tb_tk1();
$display(""); $display("");
$display("--- test11: SPI access control started."); $display("--- test11: SPI access control started.");
// Read SPI ready. Access should be blocked after reset. // Start by resetting and check if access is enabled.
$display("Status of access_ok_reg after reset: 0x%1x", dut.access_ok_reg); $display("--- test11: Check that SPI access is disabled after reset.");
reset_dut();
read_word(ADDR_SPI_XFER, 32'h0); read_word(ADDR_SPI_XFER, 32'h0);
$display("");
// Signal that we are performing access from ROM. // Set the SPI command adress API to an address in ROM space.
// Then try to read SPI ready. This should be granted. // Read it back to check that it has been set.
tb_rom_access = 1'h1; $display("--- test11: Set and read SPI command address.");
write_word(ADDR_SPI_CMD, 32'h0000dead);
read_word(ADDR_SPI_CMD, 32'h0000dead);
$display("");
// Simulate CPU instruction read from the SPI command adress.
// And check that access has been enabled.
$display("--- test11: Perform CPU instruction read from SPI command address.");
$display("--- test11: Then check that SPI access is enabled.");
tb_cpu_addr = 32'h0000dead;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(CLK_PERIOD); #(CLK_PERIOD);
tb_rom_access = 1'h0; tb_cpu_instr = 1'h0;
$display("Status of access_ok_reg after ROM access: 0x%1x", dut.access_ok_reg); tb_cpu_valid = 1'h0;
read_word(ADDR_SPI_XFER, 32'h1); read_word(ADDR_SPI_XFER, 32'h1);
$display("");
// Signal that we are performing access from RAM. // Simulate CPU instruction read from a RAM address.
// Then try to read SPI ready. This should be blocked. // And check that access has been disabled.
tb_ram_access = 1'h1; $display("--- test11: Perform CPU instruction read from a RAM address.");
$display("--- test11: Then check that SPI access has been disabled.");
tb_cpu_addr = 32'h4000dead;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(CLK_PERIOD); #(CLK_PERIOD);
tb_ram_access = 1'h0; tb_cpu_instr = 1'h0;
$display("Status of access_ok_reg after RAM access: 0x%1x", dut.access_ok_reg); tb_cpu_valid = 1'h0;
read_word(ADDR_SPI_XFER, 32'h0); read_word(ADDR_SPI_XFER, 32'h0);
$display("");
// Signal that we are performing access from ROM again.
// Then try to read SPI ready. This should be granted. // Move the SPI command adress API to a new address in ROM space.
tb_rom_access = 1'h1; // Read it back to check that it has been set.
$display("--- test11: Set SPI command address to a new address and read again.");
write_word(ADDR_SPI_CMD, 32'h0000cafe);
read_word(ADDR_SPI_CMD, 32'h0000cafe);
$display("");
// Simulate CPU instruction read from the old SPI command adress.
// And check that access is still been disabled.
$display("--- test11: Perform CPU instruction read from old SPI command address.");
$display("--- test11: Then check that SPI access is still disabled.");
tb_cpu_addr = 32'h0000dead;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(CLK_PERIOD); #(CLK_PERIOD);
tb_rom_access = 1'h0; tb_cpu_instr = 1'h0;
$display("Status of access_ok_reg after ROM access: 0x%1x", dut.access_ok_reg); tb_cpu_valid = 1'h0;
read_word(ADDR_SPI_XFER, 32'h0);
$display("");
// Simulate CPU instruction read from the new SPI command adress.
// And check that access is now enabled.
$display("--- test11: Perform CPU instruction read from new SPI command address.");
$display("--- test11: Then check that SPI access is now enabled.");
tb_cpu_addr = 32'h0000cafe;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(CLK_PERIOD);
tb_cpu_instr = 1'h0;
tb_cpu_valid = 1'h0;
read_word(ADDR_SPI_XFER, 32'h1); read_word(ADDR_SPI_XFER, 32'h1);
$display("--- test11: completed."); $display("--- test11: completed.");