From 42337778310a458272fae1ea32c34888a0be39a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Thu, 11 Jul 2024 13:21:20 +0200 Subject: [PATCH] fpga: Add testcase for SPI access control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add testcase that checks that access control is enabled and disabled as expected. Signed-off-by: Joachim Strömbergson --- hw/application_fpga/core/tk1/tb/tb_tk1.v | 104 ++++++++++++++++------- 1 file changed, 74 insertions(+), 30 deletions(-) diff --git a/hw/application_fpga/core/tk1/tb/tb_tk1.v b/hw/application_fpga/core/tk1/tb/tb_tk1.v index e5a508e..195b69d 100644 --- a/hw/application_fpga/core/tk1/tb/tb_tk1.v +++ b/hw/application_fpga/core/tk1/tb/tb_tk1.v @@ -61,6 +61,7 @@ module tb_tk1(); localparam ADDR_SPI_EN = 8'h80; localparam ADDR_SPI_XFER = 8'h81; localparam ADDR_SPI_DATA = 8'h82; + localparam ADDR_SPI_CMD = 8'h83; //---------------------------------------------------------------- @@ -130,9 +131,6 @@ module tb_tk1(); .cpu_valid(tb_cpu_valid), .force_trap(tb_force_trap), - .ram_access(tb_ram_access), - .rom_access(tb_rom_access), - .ram_aslr(tb_ram_aslr), .ram_scramble(tb_ram_scramble), @@ -272,9 +270,6 @@ module tb_tk1(); tb_cpu_valid = 1'h0; tb_cpu_trap = 1'h0; - tb_ram_access = 1'h0; - tb_rom_access = 1'h0; - tb_gpio1 = 1'h0; tb_gpio2 = 1'h0; @@ -296,8 +291,7 @@ module tb_tk1(); begin if (DEBUG) begin - $display("--- Writing 0x%08x to 0x%02x.", word, address); - $display(""); + $display("--- Write word: 0x%08x to 0x%02x.", word, address); end tb_address = address; @@ -334,13 +328,11 @@ module tb_tk1(); if (DEBUG) begin if (read_data == expected) begin - $display("--- Reading 0x%08x from 0x%02x.", read_data, address); + $display("--- Read word: 0x%08x from 0x%02x.", read_data, address); end else begin - $display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x", - read_data, address, expected); + $display("--- Read word: Error. Got 0x%08x, expected 0x%08x", read_data, address, expected); error_ctr = error_ctr + 1; end - $display(""); end end endtask // read_word @@ -654,6 +646,13 @@ module tb_tk1(); begin tc_ctr = tc_ctr + 1; + // We need to enable SPI access before testing. + dut.spi_access_ctrl_new = 1'h1; + dut.spi_access_ctrl_we = 1'h1; + #(CLK_PERIOD); + dut.spi_access_ctrl_new = 1'h0; + dut.spi_access_ctrl_we = 1'h0; + $display(""); $display("--- test10: Loopback in SPI Master started."); @@ -668,8 +667,9 @@ module tb_tk1(); $display("--- test10: Byte should have been sent."); write_word(ADDR_SPI_EN, 32'h0); - // 0x58 is the inverse of 0xa7. + // Read back data. 0x58 is the inverse of 0xa7. read_word(ADDR_SPI_DATA, 32'h58); + write_word(ADDR_SPI_EN, 32'h0); $display("--- test10: completed."); $display(""); @@ -689,32 +689,76 @@ module tb_tk1(); $display(""); $display("--- test11: SPI access control started."); - // Read SPI ready. Access should be blocked after reset. - $display("Status of access_ok_reg after reset: 0x%1x", dut.access_ok_reg); + // Start by resetting and check if access is enabled. + $display("--- test11: Check that SPI access is disabled after reset."); + reset_dut(); read_word(ADDR_SPI_XFER, 32'h0); + $display(""); - // Signal that we are performing access from ROM. - // Then try to read SPI ready. This should be granted. - tb_rom_access = 1'h1; + // Set the SPI command adress API to an address in ROM space. + // Read it back to check that it has been set. + $display("--- test11: Set and read SPI command address."); + write_word(ADDR_SPI_CMD, 32'h0000dead); + read_word(ADDR_SPI_CMD, 32'h0000dead); + $display(""); + + // Simulate CPU instruction read from the SPI command adress. + // And check that access has been enabled. + $display("--- test11: Perform CPU instruction read from SPI command address."); + $display("--- test11: Then check that SPI access is enabled."); + tb_cpu_addr = 32'h0000dead; + tb_cpu_instr = 1'h1; + tb_cpu_valid = 1'h1; #(CLK_PERIOD); - tb_rom_access = 1'h0; - $display("Status of access_ok_reg after ROM access: 0x%1x", dut.access_ok_reg); + tb_cpu_instr = 1'h0; + tb_cpu_valid = 1'h0; read_word(ADDR_SPI_XFER, 32'h1); + $display(""); - // Signal that we are performing access from RAM. - // Then try to read SPI ready. This should be blocked. - tb_ram_access = 1'h1; + // Simulate CPU instruction read from a RAM address. + // And check that access has been disabled. + $display("--- test11: Perform CPU instruction read from a RAM address."); + $display("--- test11: Then check that SPI access has been disabled."); + tb_cpu_addr = 32'h4000dead; + tb_cpu_instr = 1'h1; + tb_cpu_valid = 1'h1; #(CLK_PERIOD); - tb_ram_access = 1'h0; - $display("Status of access_ok_reg after RAM access: 0x%1x", dut.access_ok_reg); + tb_cpu_instr = 1'h0; + tb_cpu_valid = 1'h0; read_word(ADDR_SPI_XFER, 32'h0); + $display(""); - // Signal that we are performing access from ROM again. - // Then try to read SPI ready. This should be granted. - tb_rom_access = 1'h1; + + // Move the SPI command adress API to a new address in ROM space. + // Read it back to check that it has been set. + $display("--- test11: Set SPI command address to a new address and read again."); + write_word(ADDR_SPI_CMD, 32'h0000cafe); + read_word(ADDR_SPI_CMD, 32'h0000cafe); + $display(""); + + // Simulate CPU instruction read from the old SPI command adress. + // And check that access is still been disabled. + $display("--- test11: Perform CPU instruction read from old SPI command address."); + $display("--- test11: Then check that SPI access is still disabled."); + tb_cpu_addr = 32'h0000dead; + tb_cpu_instr = 1'h1; + tb_cpu_valid = 1'h1; #(CLK_PERIOD); - tb_rom_access = 1'h0; - $display("Status of access_ok_reg after ROM access: 0x%1x", dut.access_ok_reg); + tb_cpu_instr = 1'h0; + tb_cpu_valid = 1'h0; + read_word(ADDR_SPI_XFER, 32'h0); + $display(""); + + // Simulate CPU instruction read from the new SPI command adress. + // And check that access is now enabled. + $display("--- test11: Perform CPU instruction read from new SPI command address."); + $display("--- test11: Then check that SPI access is now enabled."); + tb_cpu_addr = 32'h0000cafe; + tb_cpu_instr = 1'h1; + tb_cpu_valid = 1'h1; + #(CLK_PERIOD); + tb_cpu_instr = 1'h0; + tb_cpu_valid = 1'h0; read_word(ADDR_SPI_XFER, 32'h1); $display("--- test11: completed.");