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Remove name, version from several cores

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timer
       touch_sense
       figaro
       uart
       uds
This commit is contained in:
Joachim Strömbergson 2022-10-11 09:50:45 +02:00
parent c90771fe19
commit 3f44b999ac
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
6 changed files with 13 additions and 117 deletions
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20
hw/application_fpga/core/timer/rtl/timer.v
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@ -30,10 +30,6 @@ module timer(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08; localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0; localparam CTRL_START_BIT = 0;
localparam CTRL_STOP_BIT = 1; localparam CTRL_STOP_BIT = 1;
@ -44,10 +40,6 @@ module timer(
localparam ADDR_PRESCALER = 8'h0a; localparam ADDR_PRESCALER = 8'h0a;
localparam ADDR_TIMER = 8'h0b; localparam ADDR_TIMER = 8'h0b;
localparam CORE_NAME0 = 32'h74696d65; // "time"
localparam CORE_NAME1 = 32'h72202020; // "r "
localparam CORE_VERSION = 32'h00000003;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
@ -159,18 +151,6 @@ module timer(
end end
else begin else begin
if (address == ADDR_NAME0) begin
tmp_read_data = CORE_NAME0;
end
if (address == ADDR_NAME1) begin
tmp_read_data = CORE_NAME1;
end
if (address == ADDR_VERSION) begin
tmp_read_data = CORE_VERSION;
end
if (address == ADDR_STATUS) begin if (address == ADDR_STATUS) begin
tmp_read_data = {31'h0, core_ready}; tmp_read_data = {31'h0, core_ready};
end end

20
hw/application_fpga/core/touch_sense/rtl/touch_sense.v
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@ -31,17 +31,9 @@ module touch_sense(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_EVENT_BIT = 0; localparam STATUS_EVENT_BIT = 0;
localparam CORE_NAME0 = 32'h745f7365; // "t_se"
localparam CORE_NAME1 = 32'h6e736520; // "nse "
localparam CORE_VERSION = 32'h00000001;
localparam CTRL_IDLE = 2'h0; localparam CTRL_IDLE = 2'h0;
localparam CTRL_EVENT = 2'h1; localparam CTRL_EVENT = 2'h1;
localparam CTRL_WAIT = 2'h2; localparam CTRL_WAIT = 2'h2;
@ -125,18 +117,6 @@ module touch_sense(
end end
else begin else begin
if (address == ADDR_NAME0) begin
tmp_read_data = CORE_NAME0;
end
if (address == ADDR_NAME1) begin
tmp_read_data = CORE_NAME1;
end
if (address == ADDR_VERSION) begin
tmp_read_data = CORE_VERSION;
end
if (address == ADDR_STATUS) begin if (address == ADDR_STATUS) begin
tmp_read_data[STATUS_EVENT_BIT] = touch_event_reg; tmp_read_data[STATUS_EVENT_BIT] = touch_event_reg;
end end

20
hw/application_fpga/core/trng/rtl/figaro.v
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@ -31,10 +31,6 @@ module figaro(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_STATUS = 8'h09; localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0; localparam STATUS_READY_BIT = 0;
@ -42,10 +38,6 @@ module figaro(
localparam ADDR_ENTROPY = 8'h20; localparam ADDR_ENTROPY = 8'h20;
localparam CORE_NAME0 = 32'h66696761; // "figa"
localparam CORE_NAME1 = 32'h726f2020; // "ro "
localparam CORE_VERSION = 32'h00000001;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Wires. // Wires.
@ -101,18 +93,6 @@ module figaro(
end end
else begin else begin
if (address == ADDR_NAME0) begin
tmp_read_data = CORE_NAME0;
end
if (address == ADDR_NAME1) begin
tmp_read_data = CORE_NAME1;
end
if (address == ADDR_VERSION) begin
tmp_read_data = CORE_VERSION;
end
if (address == ADDR_STATUS) begin if (address == ADDR_STATUS) begin
tmp_read_data = {31'h0, core_ready}; tmp_read_data = {31'h0, core_ready};
end end

22
hw/application_fpga/core/uart/rtl/uart.v
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@ -69,10 +69,6 @@ module uart(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_CORE_NAME0 = 8'h00;
localparam ADDR_CORE_NAME1 = 8'h01;
localparam ADDR_CORE_VERSION = 8'h02;
localparam ADDR_BIT_RATE = 8'h10; localparam ADDR_BIT_RATE = 8'h10;
localparam ADDR_DATA_BITS = 8'h11; localparam ADDR_DATA_BITS = 8'h11;
localparam ADDR_STOP_BITS = 8'h12; localparam ADDR_STOP_BITS = 8'h12;
@ -83,12 +79,6 @@ module uart(
localparam ADDR_TX_STATUS = 8'h40; localparam ADDR_TX_STATUS = 8'h40;
localparam ADDR_TX_DATA = 8'h41; localparam ADDR_TX_DATA = 8'h41;
localparam CORE_NAME0 = 32'h75617274; // "uart"
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h00000004;
// The default bit rate is based on target clock frequency // The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the // divided by the bit rate times in order to hit the
// center of the bits. I.e. // center of the bits. I.e.
@ -257,18 +247,6 @@ module uart(
else begin else begin
case (address) case (address)
ADDR_CORE_NAME0: begin
tmp_read_data = CORE_NAME0;
end
ADDR_CORE_NAME1: begin
tmp_read_data = CORE_NAME1;
end
ADDR_CORE_VERSION: begin
tmp_read_data = CORE_VERSION;
end
ADDR_BIT_RATE: begin ADDR_BIT_RATE: begin
tmp_read_data = {16'h0, bit_rate_reg}; tmp_read_data = {16'h0, bit_rate_reg};
end end

20
hw/application_fpga/core/uds/rtl/uds.v
View File

@ -29,17 +29,9 @@ module uds(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Internal constant and parameter definitions. // Internal constant and parameter definitions.
//---------------------------------------------------------------- //----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_UDS_FIRST = 8'h10; localparam ADDR_UDS_FIRST = 8'h10;
localparam ADDR_UDS_LAST = 8'h17; localparam ADDR_UDS_LAST = 8'h17;
localparam CORE_NAME0 = 32'h7564735f; // "uds_"
localparam CORE_NAME1 = 32'h6d656d20; // "mem "
localparam CORE_VERSION = 32'h00000001;
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
@ -99,18 +91,6 @@ module uds(
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (address == ADDR_NAME0) begin
tmp_read_data = CORE_NAME0;
end
if (address == ADDR_NAME1) begin
tmp_read_data = CORE_NAME1;
end
if (address == ADDR_VERSION) begin
tmp_read_data = CORE_VERSION;
end
if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
if (!fw_app_mode) begin if (!fw_app_mode) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin if (uds_rd_reg[address[2 : 0]] == 1'h0) begin

28
hw/application_fpga/core/uds/tb/tb_uds.v
View File

@ -42,6 +42,7 @@ module tb_uds();
reg tb_clk; reg tb_clk;
reg tb_reset_n; reg tb_reset_n;
reg tb_fw_app_mode;
reg tb_cs; reg tb_cs;
reg [7 : 0] tb_address; reg [7 : 0] tb_address;
wire [31 : 0] tb_read_data; wire [31 : 0] tb_read_data;
@ -53,14 +54,15 @@ module tb_uds();
// Device Under Test. // Device Under Test.
//---------------------------------------------------------------- //----------------------------------------------------------------
uds dut( uds dut(
.clk(tb_clk), .clk(tb_clk),
.reset_n(tb_reset_n), .reset_n(tb_reset_n),
.cs(tb_cs), .fw_app_mode(tb_fw_app_mode),
.address(tb_address), .cs(tb_cs),
.read_data(tb_read_data) .address(tb_address),
); .read_data(tb_read_data)
);
//---------------------------------------------------------------- //----------------------------------------------------------------
@ -161,10 +163,11 @@ module tb_uds();
tc_ctr = 0; tc_ctr = 0;
tb_monitor = 0; tb_monitor = 0;
tb_clk = 1'h0; tb_clk = 1'h0;
tb_reset_n = 1'h1; tb_reset_n = 1'h1;
tb_cs = 1'h0; tb_fw_app_mode = 1'h0;
tb_address = 8'h0; tb_cs = 1'h0;
tb_address = 8'h0;
end end
endtask // init_sim endtask // init_sim
@ -204,11 +207,6 @@ module tb_uds();
$display(""); $display("");
$display("--- test1: started."); $display("--- test1: started.");
$display("--- test1: Reading NAME and version info.");
read_word(ADDR_NAME0);
read_word(ADDR_NAME1);
read_word(ADDR_VERSION);
$display("--- test1: Dumping DUT state to show UDS contents"); $display("--- test1: Dumping DUT state to show UDS contents");
dump_dut_state(); dump_dut_state();