diff --git a/hw/application_fpga/core/timer/rtl/timer.v b/hw/application_fpga/core/timer/rtl/timer.v index 9a44e77..bc1f47c 100644 --- a/hw/application_fpga/core/timer/rtl/timer.v +++ b/hw/application_fpga/core/timer/rtl/timer.v @@ -30,10 +30,6 @@ module timer( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; - localparam ADDR_CTRL = 8'h08; localparam CTRL_START_BIT = 0; localparam CTRL_STOP_BIT = 1; @@ -44,10 +40,6 @@ module timer( localparam ADDR_PRESCALER = 8'h0a; localparam ADDR_TIMER = 8'h0b; - localparam CORE_NAME0 = 32'h74696d65; // "time" - localparam CORE_NAME1 = 32'h72202020; // "r " - localparam CORE_VERSION = 32'h00000003; - //---------------------------------------------------------------- // Registers including update variables and write enable. @@ -159,18 +151,6 @@ module timer( end else begin - if (address == ADDR_NAME0) begin - tmp_read_data = CORE_NAME0; - end - - if (address == ADDR_NAME1) begin - tmp_read_data = CORE_NAME1; - end - - if (address == ADDR_VERSION) begin - tmp_read_data = CORE_VERSION; - end - if (address == ADDR_STATUS) begin tmp_read_data = {31'h0, core_ready}; end diff --git a/hw/application_fpga/core/touch_sense/rtl/touch_sense.v b/hw/application_fpga/core/touch_sense/rtl/touch_sense.v index 754c857..6233619 100644 --- a/hw/application_fpga/core/touch_sense/rtl/touch_sense.v +++ b/hw/application_fpga/core/touch_sense/rtl/touch_sense.v @@ -31,17 +31,9 @@ module touch_sense( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; - localparam ADDR_STATUS = 8'h09; localparam STATUS_EVENT_BIT = 0; - localparam CORE_NAME0 = 32'h745f7365; // "t_se" - localparam CORE_NAME1 = 32'h6e736520; // "nse " - localparam CORE_VERSION = 32'h00000001; - localparam CTRL_IDLE = 2'h0; localparam CTRL_EVENT = 2'h1; localparam CTRL_WAIT = 2'h2; @@ -125,18 +117,6 @@ module touch_sense( end else begin - if (address == ADDR_NAME0) begin - tmp_read_data = CORE_NAME0; - end - - if (address == ADDR_NAME1) begin - tmp_read_data = CORE_NAME1; - end - - if (address == ADDR_VERSION) begin - tmp_read_data = CORE_VERSION; - end - if (address == ADDR_STATUS) begin tmp_read_data[STATUS_EVENT_BIT] = touch_event_reg; end diff --git a/hw/application_fpga/core/trng/rtl/figaro.v b/hw/application_fpga/core/trng/rtl/figaro.v index 9e28707..70ba469 100644 --- a/hw/application_fpga/core/trng/rtl/figaro.v +++ b/hw/application_fpga/core/trng/rtl/figaro.v @@ -31,10 +31,6 @@ module figaro( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; - localparam ADDR_STATUS = 8'h09; localparam STATUS_READY_BIT = 0; @@ -42,10 +38,6 @@ module figaro( localparam ADDR_ENTROPY = 8'h20; - localparam CORE_NAME0 = 32'h66696761; // "figa" - localparam CORE_NAME1 = 32'h726f2020; // "ro " - localparam CORE_VERSION = 32'h00000001; - //---------------------------------------------------------------- // Wires. @@ -101,18 +93,6 @@ module figaro( end else begin - if (address == ADDR_NAME0) begin - tmp_read_data = CORE_NAME0; - end - - if (address == ADDR_NAME1) begin - tmp_read_data = CORE_NAME1; - end - - if (address == ADDR_VERSION) begin - tmp_read_data = CORE_VERSION; - end - if (address == ADDR_STATUS) begin tmp_read_data = {31'h0, core_ready}; end diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v index b31ecd8..d84d8ec 100644 --- a/hw/application_fpga/core/uart/rtl/uart.v +++ b/hw/application_fpga/core/uart/rtl/uart.v @@ -69,10 +69,6 @@ module uart( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_CORE_NAME0 = 8'h00; - localparam ADDR_CORE_NAME1 = 8'h01; - localparam ADDR_CORE_VERSION = 8'h02; - localparam ADDR_BIT_RATE = 8'h10; localparam ADDR_DATA_BITS = 8'h11; localparam ADDR_STOP_BITS = 8'h12; @@ -83,12 +79,6 @@ module uart( localparam ADDR_TX_STATUS = 8'h40; localparam ADDR_TX_DATA = 8'h41; - - localparam CORE_NAME0 = 32'h75617274; // "uart" - localparam CORE_NAME1 = 32'h20202020; // " " - localparam CORE_VERSION = 32'h00000004; - - // The default bit rate is based on target clock frequency // divided by the bit rate times in order to hit the // center of the bits. I.e. @@ -257,18 +247,6 @@ module uart( else begin case (address) - ADDR_CORE_NAME0: begin - tmp_read_data = CORE_NAME0; - end - - ADDR_CORE_NAME1: begin - tmp_read_data = CORE_NAME1; - end - - ADDR_CORE_VERSION: begin - tmp_read_data = CORE_VERSION; - end - ADDR_BIT_RATE: begin tmp_read_data = {16'h0, bit_rate_reg}; end diff --git a/hw/application_fpga/core/uds/rtl/uds.v b/hw/application_fpga/core/uds/rtl/uds.v index 8cff428..efda3d6 100644 --- a/hw/application_fpga/core/uds/rtl/uds.v +++ b/hw/application_fpga/core/uds/rtl/uds.v @@ -29,17 +29,9 @@ module uds( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; - localparam ADDR_UDS_FIRST = 8'h10; localparam ADDR_UDS_LAST = 8'h17; - localparam CORE_NAME0 = 32'h7564735f; // "uds_" - localparam CORE_NAME1 = 32'h6d656d20; // "mem " - localparam CORE_VERSION = 32'h00000001; - //---------------------------------------------------------------- // Registers including update variables and write enable. @@ -99,18 +91,6 @@ module uds( if (cs) begin tmp_ready = 1'h1; - if (address == ADDR_NAME0) begin - tmp_read_data = CORE_NAME0; - end - - if (address == ADDR_NAME1) begin - tmp_read_data = CORE_NAME1; - end - - if (address == ADDR_VERSION) begin - tmp_read_data = CORE_VERSION; - end - if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin if (!fw_app_mode) begin if (uds_rd_reg[address[2 : 0]] == 1'h0) begin diff --git a/hw/application_fpga/core/uds/tb/tb_uds.v b/hw/application_fpga/core/uds/tb/tb_uds.v index 25799ba..353c221 100644 --- a/hw/application_fpga/core/uds/tb/tb_uds.v +++ b/hw/application_fpga/core/uds/tb/tb_uds.v @@ -42,6 +42,7 @@ module tb_uds(); reg tb_clk; reg tb_reset_n; + reg tb_fw_app_mode; reg tb_cs; reg [7 : 0] tb_address; wire [31 : 0] tb_read_data; @@ -53,14 +54,15 @@ module tb_uds(); // Device Under Test. //---------------------------------------------------------------- uds dut( - .clk(tb_clk), - .reset_n(tb_reset_n), + .clk(tb_clk), + .reset_n(tb_reset_n), - .cs(tb_cs), + .fw_app_mode(tb_fw_app_mode), - .address(tb_address), - .read_data(tb_read_data) - ); + .cs(tb_cs), + .address(tb_address), + .read_data(tb_read_data) + ); //---------------------------------------------------------------- @@ -161,10 +163,11 @@ module tb_uds(); tc_ctr = 0; tb_monitor = 0; - tb_clk = 1'h0; - tb_reset_n = 1'h1; - tb_cs = 1'h0; - tb_address = 8'h0; + tb_clk = 1'h0; + tb_reset_n = 1'h1; + tb_fw_app_mode = 1'h0; + tb_cs = 1'h0; + tb_address = 8'h0; end endtask // init_sim @@ -204,11 +207,6 @@ module tb_uds(); $display(""); $display("--- test1: started."); - $display("--- test1: Reading NAME and version info."); - read_word(ADDR_NAME0); - read_word(ADDR_NAME1); - read_word(ADDR_VERSION); - $display("--- test1: Dumping DUT state to show UDS contents"); dump_dut_state();