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Rename top level simulation files
* Rename application_fpga_vsim.v and reset_gen_vsim.v to application_fpga_sim.v and reset_gen_sim.v * Update Makefile * Fix a typo
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@ -79,8 +79,8 @@ FPGA_SRC = \
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# Verilator simulation specific source files.
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VERILATOR_FPGA_SRC = \
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$(P)/tb/application_fpga_vsim.v \
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$(P)/tb/reset_gen_vsim.v
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$(P)/tb/application_fpga_sim.v \
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$(P)/tb/reset_gen_sim.v
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# Common verilog source files.
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VERILOG_SRCS = \
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@ -1,10 +1,10 @@
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//======================================================================
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//
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// application_fpga.v
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// ------------------
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// application_fpga_sim.v
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// ----------------------
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// Top level module of the application FPGA.
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// The design exposes a UART interface to allow a host to
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// send commands and receive resposes as needed load, execute and
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// send commands and receive responses as needed load, execute and
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// communicate with applications.
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//
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//
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@ -1,6 +1,6 @@
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//======================================================================
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//
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// reset_gen_vsim.v
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// reset_gen_sim.v
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// ----------------
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// Reset generator Verilator simulation of the application_fpga.
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//
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