From 330146ba3a23d5a7e812f1737651884abca115d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Th=C3=B6rnblad?= Date: Tue, 12 Nov 2024 14:29:20 +0100 Subject: [PATCH] Rename top level simulation files * Rename application_fpga_vsim.v and reset_gen_vsim.v to application_fpga_sim.v and reset_gen_sim.v * Update Makefile * Fix a typo --- hw/application_fpga/Makefile | 4 ++-- .../tb/{application_fpga_vsim.v => application_fpga_sim.v} | 6 +++--- .../tb/{reset_gen_vsim.v => reset_gen_sim.v} | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) rename hw/application_fpga/tb/{application_fpga_vsim.v => application_fpga_sim.v} (99%) rename hw/application_fpga/tb/{reset_gen_vsim.v => reset_gen_sim.v} (98%) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index 784d410..d2fe02b 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -79,8 +79,8 @@ FPGA_SRC = \ # Verilator simulation specific source files. VERILATOR_FPGA_SRC = \ - $(P)/tb/application_fpga_vsim.v \ - $(P)/tb/reset_gen_vsim.v + $(P)/tb/application_fpga_sim.v \ + $(P)/tb/reset_gen_sim.v # Common verilog source files. VERILOG_SRCS = \ diff --git a/hw/application_fpga/tb/application_fpga_vsim.v b/hw/application_fpga/tb/application_fpga_sim.v similarity index 99% rename from hw/application_fpga/tb/application_fpga_vsim.v rename to hw/application_fpga/tb/application_fpga_sim.v index e259e16..3f94871 100644 --- a/hw/application_fpga/tb/application_fpga_vsim.v +++ b/hw/application_fpga/tb/application_fpga_sim.v @@ -1,10 +1,10 @@ //====================================================================== // -// application_fpga.v -// ------------------ +// application_fpga_sim.v +// ---------------------- // Top level module of the application FPGA. // The design exposes a UART interface to allow a host to -// send commands and receive resposes as needed load, execute and +// send commands and receive responses as needed load, execute and // communicate with applications. // // diff --git a/hw/application_fpga/tb/reset_gen_vsim.v b/hw/application_fpga/tb/reset_gen_sim.v similarity index 98% rename from hw/application_fpga/tb/reset_gen_vsim.v rename to hw/application_fpga/tb/reset_gen_sim.v index c7a2987..6187d4c 100644 --- a/hw/application_fpga/tb/reset_gen_vsim.v +++ b/hw/application_fpga/tb/reset_gen_sim.v @@ -1,6 +1,6 @@ //====================================================================== // -// reset_gen_vsim.v +// reset_gen_sim.v // ---------------- // Reset generator Verilator simulation of the application_fpga. //