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Add flag to control of SPI master is included in build 

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-04-15 10:50:51 +02:00
parent 0aabebd71e
commit 32f7ebc7ad
No known key found for this signature in database
GPG Key ID: 865B8A548EA61679
1 changed files with 2 additions and 2 deletions
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4
hw/application_fpga/Makefile
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@ -213,10 +213,10 @@ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
# Main FPGA build flow.
# Synthesis. Place & Route. Bitstream generation.
#
# For minimal SPI-master add flag -DINCLUDE_SPI_MASTER to Yosys.
# For minimal SPI-master add flag -DINCLUDE_SPI_MASTER to Yosys cmd.
#-------------------------------------------------------------------
synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
$(YOSYS_PATH)yosys -v3 -l synth.log -DINCLUDE_SPI_MASTER -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
-DUDS_HEX=\"$(P)/data/uds.hex\" \
-DUDI_HEX=\"$(P)/data/udi.hex\" \