From 32f7ebc7ad5a1155962e613c4f96c8f3054901aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 15 Apr 2024 10:50:51 +0200 Subject: [PATCH] Add flag to control of SPI master is included in build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index 64fec65..a77ae9f 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -213,10 +213,10 @@ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS) # Main FPGA build flow. # Synthesis. Place & Route. Bitstream generation. # -# For minimal SPI-master add flag -DINCLUDE_SPI_MASTER to Yosys. +# For minimal SPI-master add flag -DINCLUDE_SPI_MASTER to Yosys cmd. #------------------------------------------------------------------- synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex - $(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ + $(YOSYS_PATH)yosys -v3 -l synth.log -DINCLUDE_SPI_MASTER -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \ -DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \ -DUDS_HEX=\"$(P)/data/uds.hex\" \ -DUDI_HEX=\"$(P)/data/udi.hex\" \