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Joachim Strömbergson 2022-09-19 10:02:58 +02:00
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@ -33,6 +33,7 @@ The first implementation is the Tillitis Key 1:
* [Firmware](hw/application_fpga/fw/mta1_mkdf/README.md)
* [Toolchain setup](doc/toolchain_setup.md)
* [Quickstart](doc/quickstart.md) to program the Tillitis Key1
* [Release Notes](doc/release_notes.md)
## About this repository

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# Release Notes
## engineering-release-1
### Hardware
#### Limitations
- The entropy generated by the TRNG has not yet been thoroughly tested, and the generator has not been adjusted to generate good, unbiased randomness. Any application that wants to use the entropy source SHOULD NOT use the output directly, but only as seed to a Digital Random Bit Generator (DRBG), such as Hash_DRBG.
- The UART is currently running at 38400 bps. Future releases will increase the bitrate when communication at higher bitrates has been verified as stable and error free.
- The internal clock frequency is currently limited to 12 MHz. Future releases will increase the clock frequency to provide improved performance.
- The functionality in the firmware is currently not exposed to the applications via a stable name space, API. Future releases will provide access to FW functions such as the BLAKE2s hash function.
- The timer currently does not include a timeout interrupt. Applications using the timer must check the status in order to detect a timeout event.
- The timer currently does not provide a set of typical settings. Applications using the timer must set timer and prescaler as needed to get the desired time given the current clock speed.