From 2bb62af1832871e62d56aa5db2055bda99f9d41e Mon Sep 17 00:00:00 2001
From: Daniel Lublin <daniel@lublin.se>
Date: Mon, 3 Oct 2022 13:11:53 +0200
Subject: [PATCH] Update bit divisor calc in verilator's uart to our current 18
 MHz

---
 hw/application_fpga/tb/application_fpga_verilator.cc | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/hw/application_fpga/tb/application_fpga_verilator.cc b/hw/application_fpga/tb/application_fpga_verilator.cc
index 46c50c3..f7a4b33 100644
--- a/hw/application_fpga/tb/application_fpga_verilator.cc
+++ b/hw/application_fpga/tb/application_fpga_verilator.cc
@@ -24,10 +24,9 @@
 #include "Vapplication_fpga.h"
 #include "verilated.h"
 
-// Joachim says:
-// Clock: 12 MHz, 38400 bps
-// Divisor = 12*10E6 / 38400 = 312
-#define BIT_DIV 312
+// Clock: 18 MHz, 38400 bps
+// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
+#define BIT_DIV 469
 
 struct uart {
 	int bit_div;