Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-12-25 15:39:27 -05:00
Code Issues Packages Projects Releases Wiki Activity

Rename rosc.v to trng.v

Browse Source
This commit is contained in:
Jonas Thörnblad 2024-11-13 15:53:00 +01:00
parent 49189a3ba7
commit 2364466a9e
No known key found for this signature in database
GPG Key ID: 2D318AD00A326F95
3 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/application_fpga/Makefile
View File

@ -98,7 +98,7 @@ VERILOG_SRCS = \
$(P)/core/uart/rtl/uart_core.v \ $(P)/core/uart/rtl/uart_core.v \
$(P)/core/uart/rtl/uart_fifo.v \ $(P)/core/uart/rtl/uart_fifo.v \
$(P)/core/uart/rtl/uart.v \ $(P)/core/uart/rtl/uart.v \
$(P)/core/trng/rtl/rosc.v $(P)/core/trng/rtl/trng.v
# PicoRV32 verilog source file # PicoRV32 verilog source file
PICORV32_SRCS = \ PICORV32_SRCS = \

0
hw/application_fpga/core/trng/rtl/rosc.v → hw/application_fpga/core/trng/rtl/trng.v
View File

2
hw/application_fpga/core/trng/toolruns/Makefile
View File

@ -11,7 +11,7 @@
# #
#=================================================================== #===================================================================
TOP_SRC=../rtl/rosc.v TOP_SRC=../rtl/trng.v
TB_TOP_SRC =../tb/tb_trng.v ../tb/SB_LUT4.v TB_TOP_SRC =../tb/tb_trng.v ../tb/SB_LUT4.v
CC = iverilog CC = iverilog