From 2364466a9ea19c39773b433468080649aece9905 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Th=C3=B6rnblad?= Date: Wed, 13 Nov 2024 15:53:00 +0100 Subject: [PATCH] Rename rosc.v to trng.v --- hw/application_fpga/Makefile | 2 +- hw/application_fpga/core/trng/rtl/{rosc.v => trng.v} | 0 hw/application_fpga/core/trng/toolruns/Makefile | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename hw/application_fpga/core/trng/rtl/{rosc.v => trng.v} (100%) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index d2fe02b..ab7b1bf 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -98,7 +98,7 @@ VERILOG_SRCS = \ $(P)/core/uart/rtl/uart_core.v \ $(P)/core/uart/rtl/uart_fifo.v \ $(P)/core/uart/rtl/uart.v \ - $(P)/core/trng/rtl/rosc.v + $(P)/core/trng/rtl/trng.v # PicoRV32 verilog source file PICORV32_SRCS = \ diff --git a/hw/application_fpga/core/trng/rtl/rosc.v b/hw/application_fpga/core/trng/rtl/trng.v similarity index 100% rename from hw/application_fpga/core/trng/rtl/rosc.v rename to hw/application_fpga/core/trng/rtl/trng.v diff --git a/hw/application_fpga/core/trng/toolruns/Makefile b/hw/application_fpga/core/trng/toolruns/Makefile index dff7b30..81374f6 100755 --- a/hw/application_fpga/core/trng/toolruns/Makefile +++ b/hw/application_fpga/core/trng/toolruns/Makefile @@ -11,7 +11,7 @@ # #=================================================================== -TOP_SRC=../rtl/rosc.v +TOP_SRC=../rtl/trng.v TB_TOP_SRC =../tb/tb_trng.v ../tb/SB_LUT4.v CC = iverilog