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Renamed sb_rgba_drv.v to sb_rgba_drv_sim.v

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Jonas Thörnblad 2024-11-13 14:37:20 +01:00
parent 2b89b28b82
commit 1ea5db1179
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GPG Key ID: 2D318AD00A326F95
2 changed files with 4 additions and 4 deletions
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4
hw/application_fpga/core/tk1/tb/sb_rgba_drv.v → hw/application_fpga/core/tk1/tb/sb_rgba_drv_sim.v
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@ -1,6 +1,6 @@
//======================================================================
//
// SB_RGBA_DRV.v
// sb_rgba_drv_sim.v
// -------------
// Dummy version of the SB_RGBA_DRV hard macro in Lattice iCE40 UP
// devices. This is just to be able to build the testbench. The only
@ -44,5 +44,5 @@ module SB_RGBA_DRV (
endmodule // SB_RGBA_DRV
//======================================================================
// EOF SB_RGBA_DRV.v
// EOF sb_rgba_drv_sim.v
//======================================================================

4
hw/application_fpga/core/tk1/toolruns/Makefile
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@ -16,8 +16,8 @@ TB_SPI_SRC =../tb/tb_tk1_spi_master.v
MEM_MODEL_SRC =../tb/W25Q80DL.v
TOP_SRC=../rtl/tk1.v $(SPI_SRC)
TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
LINT_SRC=$(TOP_SRC) ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv_sim.v ../tb/udi_rom_sim.v
LINT_SRC=$(TOP_SRC) ../tb/sb_rgba_drv_sim.v ../tb/udi_rom_sim.v
CC = iverilog
CC_FLAGS = -Wall