diff --git a/hw/application_fpga/core/tk1/tb/sb_rgba_drv.v b/hw/application_fpga/core/tk1/tb/sb_rgba_drv_sim.v
similarity index 96%
rename from hw/application_fpga/core/tk1/tb/sb_rgba_drv.v
rename to hw/application_fpga/core/tk1/tb/sb_rgba_drv_sim.v
index 6803538..3a1bd8b 100644
--- a/hw/application_fpga/core/tk1/tb/sb_rgba_drv.v
+++ b/hw/application_fpga/core/tk1/tb/sb_rgba_drv_sim.v
@@ -1,6 +1,6 @@
 //======================================================================
 //
-// SB_RGBA_DRV.v
+// sb_rgba_drv_sim.v
 // -------------
 // Dummy version of the SB_RGBA_DRV hard macro in Lattice iCE40 UP
 // devices. This is just to be able to build the testbench. The only
@@ -44,5 +44,5 @@ module SB_RGBA_DRV (
 endmodule  // SB_RGBA_DRV
 
 //======================================================================
-// EOF SB_RGBA_DRV.v
+// EOF sb_rgba_drv_sim.v
 //======================================================================
diff --git a/hw/application_fpga/core/tk1/toolruns/Makefile b/hw/application_fpga/core/tk1/toolruns/Makefile
index 51d9312..96eab04 100755
--- a/hw/application_fpga/core/tk1/toolruns/Makefile
+++ b/hw/application_fpga/core/tk1/toolruns/Makefile
@@ -16,8 +16,8 @@ TB_SPI_SRC =../tb/tb_tk1_spi_master.v
 MEM_MODEL_SRC =../tb/W25Q80DL.v
 
 TOP_SRC=../rtl/tk1.v $(SPI_SRC)
-TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
-LINT_SRC=$(TOP_SRC) ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
+TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv_sim.v ../tb/udi_rom_sim.v
+LINT_SRC=$(TOP_SRC) ../tb/sb_rgba_drv_sim.v ../tb/udi_rom_sim.v
 
 CC = iverilog
 CC_FLAGS = -Wall