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Updated README, completed testcase and cleaned up the testbench

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2023-05-03 14:53:34 +02:00 committed by dehanj
parent de7f273f71
commit 1e97e27e66
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GPG Key ID: 3707A9DBF4BB8F1A
2 changed files with 77 additions and 36 deletions
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18
hw/application_fpga/core/uds/README.txt
View File

@ -3,5 +3,19 @@
Unique Device Secret core
## Introduction
This core store and protect the Unique Device Secret. The
storage is implemented in discrete registers. The contents can be read once between chip reset, and only if the system is in not in application access mode.
This core store and protect the Unique Device Secret (UDS) asset. The
UDS can be accessed as eight separate 32-bit words. The words can be
accessed in any order, but a given word can only be accessed once
between reset cycles. The words can only be accessed as long as the
fw_app_mode input is low, implying that the CPU is executing the FW.
Each UDS words has a companion read bit that is set when the word is
accessed. This means that the even if the chip select (cs) control
input is forced high, the content will become all zero when the read
bit has been set after one cycle.
## Implementation
The UDS words are implemented in discrete registers.

81
hw/application_fpga/core/uds/tb/tb_uds.v
View File

@ -19,15 +19,10 @@ module tb_uds();
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_UDS_FIRST = 8'h10;
localparam ADDR_UDS_LAST = 8'h17;
@ -47,8 +42,6 @@ module tb_uds();
reg [7 : 0] tb_address;
wire [31 : 0] tb_read_data;
reg [31 : 0] read_data;
//----------------------------------------------------------------
// Device Under Test.
@ -102,13 +95,19 @@ module tb_uds();
task dump_dut_state;
begin : dump_dut_state
integer i;
$display("State of DUT");
$display("State of DUT at cycle: %08d", cycle_ctr);
$display("------------");
$display("Cycle: %08d", cycle_ctr);
$display("Inputs and outputs:");
$display("fw_app_mode: 0x%1x", tb_fw_app_mode);
$display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data);
$display("");
$display("Internal state:");
$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
for (i = 0 ; i < 8 ; i = i + 1) begin
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x",
i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
$display("uds_reg[%1d]: 0x%08x, uds_rd_reg[%1d]: 0x%1x", i, dut.uds_reg[i], i, dut.uds_rd_reg[i]);
end
$display("");
$display("");
end
@ -180,12 +179,17 @@ module tb_uds();
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
begin : read_word
reg [31 : 0] read_data;
tb_address = address;
tb_cs = 1;
#(CLK_PERIOD);
tb_cs = 1'h1;
#(CLK_HALF_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
#(CLK_HALF_PERIOD);
tb_cs = 1'h0;
if (DEBUG)
begin
@ -202,11 +206,20 @@ module tb_uds();
task test1;
begin
tc_ctr = tc_ctr + 1;
tb_monitor = 1'h0;
$display("");
$display("--- test1: started.");
$display("--- test1: Filling uds with known values.");
dut.uds_reg[0] = 32'hf0f0f0f0;
dut.uds_reg[1] = 32'he1e1e1e1;
dut.uds_reg[2] = 32'hd2d2d2d2;
dut.uds_reg[3] = 32'hc3c3c3c3;
dut.uds_reg[4] = 32'hb4b4b4b4;
dut.uds_reg[5] = 32'ha5a5a5a5;
dut.uds_reg[6] = 32'h96969696;
dut.uds_reg[7] = 32'h87878787;
$display("--- test1: Dumping DUT state to show UDS contents");
dump_dut_state();
@ -229,6 +242,7 @@ module tb_uds();
dump_dut_state();
$display("--- test1: Reading UDS words again.");
$display("--- test1: This should return all zeros.");
read_word(ADDR_UDS_FIRST + 0);
read_word(ADDR_UDS_FIRST + 1);
read_word(ADDR_UDS_FIRST + 2);
@ -239,22 +253,35 @@ module tb_uds();
read_word(ADDR_UDS_FIRST + 7);
$display("--- test1: Resetting DUT.");
$display("--- test1: This should allow access again.");
reset_dut();
$display("--- test1: Filling uds with new known values.");
dut.uds_reg[0] = 32'h0f0f0f0f;
dut.uds_reg[1] = 32'h1e1e1e1e;
dut.uds_reg[2] = 32'h2d2d2d2d;
dut.uds_reg[3] = 32'h3c3c3c3c;
dut.uds_reg[4] = 32'h4b4b4b4b;
dut.uds_reg[5] = 32'h5a5a5a5a;
dut.uds_reg[6] = 32'h69696969;
dut.uds_reg[7] = 32'h78787878;
$display("--- test1: Dumping state again to see read bits.");
dump_dut_state();
$display("--- test1: Reading UDS words.");
read_word(ADDR_UDS_FIRST + 0);
read_word(ADDR_UDS_FIRST + 1);
read_word(ADDR_UDS_FIRST + 2);
read_word(ADDR_UDS_FIRST + 3);
read_word(ADDR_UDS_FIRST + 4);
read_word(ADDR_UDS_FIRST + 5);
read_word(ADDR_UDS_FIRST + 6);
$display("--- test1: Reading UDS words in changed order.");
read_word(ADDR_UDS_FIRST + 7);
read_word(ADDR_UDS_FIRST + 6);
read_word(ADDR_UDS_FIRST + 4);
read_word(ADDR_UDS_FIRST + 3);
read_word(ADDR_UDS_FIRST + 1);
read_word(ADDR_UDS_FIRST + 0);
read_word(ADDR_UDS_FIRST + 5);
read_word(ADDR_UDS_FIRST + 2);
$display("--- test1: Reading UDS words again.");
$display("--- test1: This should return all zeros.");
read_word(ADDR_UDS_FIRST + 0);
read_word(ADDR_UDS_FIRST + 1);
read_word(ADDR_UDS_FIRST + 2);
@ -267,7 +294,7 @@ module tb_uds();
$display("--- test1: completed.");
$display("");
end
endtask // tes1
endtask // test1
//----------------------------------------------------------------
@ -286,8 +313,8 @@ module tb_uds();
display_test_result();
$display("");
$display(" -= Testbench for uds started =-");
$display(" ===========================");
$display(" -= Testbench for uds completed =-");
$display(" =============================");
$display("");
$finish;
end // uds_test