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Update linter to Verilog-2005
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@ -174,7 +174,7 @@ check-binary-hashes:
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# Source linting.
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# Source linting.
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#-------------------------------------------------------------------
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#-------------------------------------------------------------------
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LINT=verilator
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LINT=verilator
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LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-DECLFILENAME \
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LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-DECLFILENAME \
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--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
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--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
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lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
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lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
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