From 1e34ddcfa623b292c098f2addacf72286f940e06 Mon Sep 17 00:00:00 2001 From: dehanj Date: Tue, 19 Mar 2024 10:45:37 +0100 Subject: [PATCH] Update linter to Verilog-2005 --- hw/application_fpga/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index 350e66d..5df5296 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -174,7 +174,7 @@ check-binary-hashes: # Source linting. #------------------------------------------------------------------- LINT=verilator -LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-DECLFILENAME \ +LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-DECLFILENAME \ --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)