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Update linter to Verilog-2005

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dehanj 2024-03-19 10:45:37 +01:00
parent 746d7f0e0d
commit 1e34ddcfa6
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hw/application_fpga/Makefile
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@ -174,7 +174,7 @@ check-binary-hashes:
# Source linting. # Source linting.
#------------------------------------------------------------------- #-------------------------------------------------------------------
LINT=verilator LINT=verilator
LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-DECLFILENAME \ LINT_FLAGS = +1364-2005ext+ --lint-only -Wall -Wno-DECLFILENAME \
--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS) lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)