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fpga/ch552: Swap fpga_cts and ch552_cts pins

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The FPGA uwg30 package cannot use B3 as an input when an instance of
SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from
here on fpga_cts) an output.

For more info check out:
FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1
PLL Placement Rules"
This commit is contained in:
Mikael Ågren 2025-05-09 17:29:52 +02:00
parent 45af9146d6
commit 1e20dba10a
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3 changed files with 6 additions and 6 deletions
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4
hw/application_fpga/data/application_fpga_tk1.pcf
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@ -14,8 +14,8 @@
# UART.
set_io interface_rx 26
set_io interface_tx 25
set_io interface_ch552_cts 27
set_io interface_fpga_cts 28
set_io interface_ch552_cts 28
set_io interface_fpga_cts 27
# SPI master to flash memory.