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Zero extend the address to match SB_RAM4K ports

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Joachim Strömbergson 2022-11-09 15:05:03 +01:00
parent 517fafff57
commit 159b20fa4e
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GPG Key ID: 865B8A548EA61679
1 changed files with 4 additions and 4 deletions
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8
hw/application_fpga/rtl/fw_ram.v
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@ -49,11 +49,11 @@ module fw_ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
SB_RAM40_4K fw_ram0( SB_RAM40_4K fw_ram0(
.RDATA(mem_read_data[15 : 0]), .RDATA(mem_read_data[15 : 0]),
.RADDR(address), .RADDR({3'h0, address}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs), .RE(fw_app_cs),
.WADDR(address), .WADDR({3'h0, address}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[15 : 0]), .WDATA(write_data[15 : 0]),
@ -64,11 +64,11 @@ module fw_ram(
SB_RAM40_4K fw_ram1( SB_RAM40_4K fw_ram1(
.RDATA(mem_read_data[31 : 16]), .RDATA(mem_read_data[31 : 16]),
.RADDR(address), .RADDR({3'h0, address}),
.RCLK(clk), .RCLK(clk),
.RCLKE(1'h1), .RCLKE(1'h1),
.RE(fw_app_cs), .RE(fw_app_cs),
.WADDR(address), .WADDR({3'h0, address}),
.WCLK(clk), .WCLK(clk),
.WCLKE(1'h1), .WCLKE(1'h1),
.WDATA(write_data[31 : 16]), .WDATA(write_data[31 : 16]),