From 159b20fa4eb5aad79e74f115407dcee64cc44bc9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Wed, 9 Nov 2022 15:05:03 +0100 Subject: [PATCH] Zero extend the address to match SB_RAM4K ports --- hw/application_fpga/rtl/fw_ram.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/application_fpga/rtl/fw_ram.v b/hw/application_fpga/rtl/fw_ram.v index 8bf948a..fd12e37 100644 --- a/hw/application_fpga/rtl/fw_ram.v +++ b/hw/application_fpga/rtl/fw_ram.v @@ -49,11 +49,11 @@ module fw_ram( //---------------------------------------------------------------- SB_RAM40_4K fw_ram0( .RDATA(mem_read_data[15 : 0]), - .RADDR(address), + .RADDR({3'h0, address}), .RCLK(clk), .RCLKE(1'h1), .RE(fw_app_cs), - .WADDR(address), + .WADDR({3'h0, address}), .WCLK(clk), .WCLKE(1'h1), .WDATA(write_data[15 : 0]), @@ -64,11 +64,11 @@ module fw_ram( SB_RAM40_4K fw_ram1( .RDATA(mem_read_data[31 : 16]), - .RADDR(address), + .RADDR({3'h0, address}), .RCLK(clk), .RCLKE(1'h1), .RE(fw_app_cs), - .WADDR(address), + .WADDR({3'h0, address}), .WCLK(clk), .WCLKE(1'h1), .WDATA(write_data[31 : 16]),