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Increase size of RX-FIFO to 512 bytes

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Joachim Strömbergson 2022-10-28 12:48:13 +02:00
parent 85ef93cd3c
commit 0eacbca2f9
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GPG Key ID: 865B8A548EA61679
1 changed files with 13 additions and 13 deletions
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26
hw/application_fpga/core/uart/rtl/uart_fifo.v
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@ -52,19 +52,19 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Registers including update variables and write enable. // Registers including update variables and write enable.
//---------------------------------------------------------------- //----------------------------------------------------------------
reg [7 : 0] fifo_mem [0 : 255]; reg [7 : 0] fifo_mem [0 : 511];
reg fifo_mem_we; reg fifo_mem_we;
reg [7: 0] in_ptr_reg; reg [8: 0] in_ptr_reg;
reg [7: 0] in_ptr_new; reg [8: 0] in_ptr_new;
reg in_ptr_we; reg in_ptr_we;
reg [7: 0] out_ptr_reg; reg [8: 0] out_ptr_reg;
reg [7: 0] out_ptr_new; reg [8: 0] out_ptr_new;
reg out_ptr_we; reg out_ptr_we;
reg [7: 0] byte_ctr_reg; reg [8: 0] byte_ctr_reg;
reg [7: 0] byte_ctr_new; reg [8: 0] byte_ctr_new;
reg byte_ctr_inc; reg byte_ctr_inc;
reg byte_ctr_dec; reg byte_ctr_dec;
reg byte_ctr_we; reg byte_ctr_we;
@ -88,9 +88,9 @@ module uart_fifo(
always @ (posedge clk) always @ (posedge clk)
begin: reg_update begin: reg_update
if (!reset_n) begin if (!reset_n) begin
in_ptr_reg <= 8'h0; in_ptr_reg <= 9'h0;
out_ptr_reg <= 8'h0; out_ptr_reg <= 9'h0;
byte_ctr_reg <= 8'h0; byte_ctr_reg <= 9'h0;
in_ack_reg <= 1'h0; in_ack_reg <= 1'h0;
end end
else begin else begin
@ -120,7 +120,7 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @*
begin : byte_ctr begin : byte_ctr
byte_ctr_new = 8'h0; byte_ctr_new = 9'h0;
byte_ctr_we = 1'h0; byte_ctr_we = 1'h0;
if ((byte_ctr_inc) && (!byte_ctr_dec)) begin if ((byte_ctr_inc) && (!byte_ctr_dec)) begin
@ -146,7 +146,7 @@ module uart_fifo(
in_ptr_new = in_ptr_reg + 1'h1; in_ptr_new = in_ptr_reg + 1'h1;
in_ptr_we = 1'h0; in_ptr_we = 1'h0;
if ((in_syn) && (!in_ack) && (byte_ctr_reg < 8'hff)) begin if ((in_syn) && (!in_ack) && (byte_ctr_reg < 9'h1ff)) begin
fifo_mem_we = 1'h1; fifo_mem_we = 1'h1;
in_ack_new = 1'h1; in_ack_new = 1'h1;
byte_ctr_inc = 1'h1; byte_ctr_inc = 1'h1;
@ -164,7 +164,7 @@ module uart_fifo(
out_ptr_new = out_ptr_reg + 1'h1; out_ptr_new = out_ptr_reg + 1'h1;
out_ptr_we = 1'h0; out_ptr_we = 1'h0;
if ((out_ack) && (byte_ctr_reg > 8'h0)) begin if ((out_ack) && (byte_ctr_reg > 9'h0)) begin
byte_ctr_dec = 1'h1; byte_ctr_dec = 1'h1;
out_ptr_we = 1'h1; out_ptr_we = 1'h1;
end end