From 0eacbca2f9f75b7a591f44a362b2171949c8bc9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Fri, 28 Oct 2022 12:48:13 +0200 Subject: [PATCH] Increase size of RX-FIFO to 512 bytes --- hw/application_fpga/core/uart/rtl/uart_fifo.v | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v index 11fa3dd..9d07602 100644 --- a/hw/application_fpga/core/uart/rtl/uart_fifo.v +++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v @@ -52,19 +52,19 @@ module uart_fifo( //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- - reg [7 : 0] fifo_mem [0 : 255]; + reg [7 : 0] fifo_mem [0 : 511]; reg fifo_mem_we; - reg [7: 0] in_ptr_reg; - reg [7: 0] in_ptr_new; + reg [8: 0] in_ptr_reg; + reg [8: 0] in_ptr_new; reg in_ptr_we; - reg [7: 0] out_ptr_reg; - reg [7: 0] out_ptr_new; + reg [8: 0] out_ptr_reg; + reg [8: 0] out_ptr_new; reg out_ptr_we; - reg [7: 0] byte_ctr_reg; - reg [7: 0] byte_ctr_new; + reg [8: 0] byte_ctr_reg; + reg [8: 0] byte_ctr_new; reg byte_ctr_inc; reg byte_ctr_dec; reg byte_ctr_we; @@ -88,9 +88,9 @@ module uart_fifo( always @ (posedge clk) begin: reg_update if (!reset_n) begin - in_ptr_reg <= 8'h0; - out_ptr_reg <= 8'h0; - byte_ctr_reg <= 8'h0; + in_ptr_reg <= 9'h0; + out_ptr_reg <= 9'h0; + byte_ctr_reg <= 9'h0; in_ack_reg <= 1'h0; end else begin @@ -120,7 +120,7 @@ module uart_fifo( //---------------------------------------------------------------- always @* begin : byte_ctr - byte_ctr_new = 8'h0; + byte_ctr_new = 9'h0; byte_ctr_we = 1'h0; if ((byte_ctr_inc) && (!byte_ctr_dec)) begin @@ -146,7 +146,7 @@ module uart_fifo( in_ptr_new = in_ptr_reg + 1'h1; in_ptr_we = 1'h0; - if ((in_syn) && (!in_ack) && (byte_ctr_reg < 8'hff)) begin + if ((in_syn) && (!in_ack) && (byte_ctr_reg < 9'h1ff)) begin fifo_mem_we = 1'h1; in_ack_new = 1'h1; byte_ctr_inc = 1'h1; @@ -164,7 +164,7 @@ module uart_fifo( out_ptr_new = out_ptr_reg + 1'h1; out_ptr_we = 1'h0; - if ((out_ack) && (byte_ctr_reg > 8'h0)) begin + if ((out_ack) && (byte_ctr_reg > 9'h0)) begin byte_ctr_dec = 1'h1; out_ptr_we = 1'h1; end