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https://github.com/tillitis/tillitis-key1.git
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FPGA: Experimental increase in SPI clock frequency
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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@ -47,10 +47,8 @@ module tk1_spi_master(
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//----------------------------------------------------------------
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localparam CTRL_IDLE = 3'h0;
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localparam CTRL_POS_FLANK = 3'h1;
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localparam CTRL_WAIT_POS = 3'h2;
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localparam CTRL_NEG_FLANK = 3'h3;
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localparam CTRL_WAIT_NEG = 3'h4;
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localparam CTRL_NEXT = 3'h5;
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localparam CTRL_NEG_FLANK = 3'h2;
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localparam CTRL_NEXT = 3'h3;
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localparam SPI_CLK_CYCLES = 4'h1;
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@ -289,31 +287,15 @@ module tk1_spi_master(
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spi_rx_data_nxt = 1'h1;
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spi_csk_new = 1'h1;
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spi_csk_we = 1'h1;
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spi_clk_ctr_rst = 1'h1;
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spi_ctrl_new = CTRL_WAIT_POS;
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spi_ctrl_we = 1'h1;
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end
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CTRL_WAIT_POS: begin
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if (spi_clk_cycles_reached) begin
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spi_ctrl_new = CTRL_NEG_FLANK;
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spi_ctrl_we = 1'h1;
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end
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end
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CTRL_NEG_FLANK: begin
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spi_csk_new = 1'h0;
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spi_csk_we = 1'h1;
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spi_clk_ctr_rst = 1'h1;
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spi_ctrl_new = CTRL_WAIT_NEG;
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spi_ctrl_new = CTRL_NEG_FLANK;
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spi_ctrl_we = 1'h1;
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end
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CTRL_WAIT_NEG: begin
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if (spi_clk_cycles_reached) begin
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spi_ctrl_new = CTRL_NEXT;
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spi_ctrl_we = 1'h1;
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end
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CTRL_NEG_FLANK: begin
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spi_csk_new = 1'h0;
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spi_csk_we = 1'h1;
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spi_ctrl_new = CTRL_NEXT;
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spi_ctrl_we = 1'h1;
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end
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CTRL_NEXT: begin
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