From 0e9df05ad03bd15d5164be979bf9ddd9c28f64a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Tue, 18 Jun 2024 13:14:28 +0200 Subject: [PATCH] FPGA: Experimental increase in SPI clock frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- .../core/tk1/rtl/tk1_spi_master.v | 34 +++++-------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/hw/application_fpga/core/tk1/rtl/tk1_spi_master.v b/hw/application_fpga/core/tk1/rtl/tk1_spi_master.v index c6b83c0..4046b51 100644 --- a/hw/application_fpga/core/tk1/rtl/tk1_spi_master.v +++ b/hw/application_fpga/core/tk1/rtl/tk1_spi_master.v @@ -47,10 +47,8 @@ module tk1_spi_master( //---------------------------------------------------------------- localparam CTRL_IDLE = 3'h0; localparam CTRL_POS_FLANK = 3'h1; - localparam CTRL_WAIT_POS = 3'h2; - localparam CTRL_NEG_FLANK = 3'h3; - localparam CTRL_WAIT_NEG = 3'h4; - localparam CTRL_NEXT = 3'h5; + localparam CTRL_NEG_FLANK = 3'h2; + localparam CTRL_NEXT = 3'h3; localparam SPI_CLK_CYCLES = 4'h1; @@ -289,31 +287,15 @@ module tk1_spi_master( spi_rx_data_nxt = 1'h1; spi_csk_new = 1'h1; spi_csk_we = 1'h1; - spi_clk_ctr_rst = 1'h1; - spi_ctrl_new = CTRL_WAIT_POS; - spi_ctrl_we = 1'h1; - end - - CTRL_WAIT_POS: begin - if (spi_clk_cycles_reached) begin - spi_ctrl_new = CTRL_NEG_FLANK; - spi_ctrl_we = 1'h1; - end - end - - CTRL_NEG_FLANK: begin - spi_csk_new = 1'h0; - spi_csk_we = 1'h1; - spi_clk_ctr_rst = 1'h1; - spi_ctrl_new = CTRL_WAIT_NEG; + spi_ctrl_new = CTRL_NEG_FLANK; spi_ctrl_we = 1'h1; end - CTRL_WAIT_NEG: begin - if (spi_clk_cycles_reached) begin - spi_ctrl_new = CTRL_NEXT; - spi_ctrl_we = 1'h1; - end + CTRL_NEG_FLANK: begin + spi_csk_new = 1'h0; + spi_csk_we = 1'h1; + spi_ctrl_new = CTRL_NEXT; + spi_ctrl_we = 1'h1; end CTRL_NEXT: begin