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PoC: fpga: Revert back to 21 MHz
To avoid having to find a new nextpnr seed, for small changes, during development
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@ -28,7 +28,7 @@ ICESTORM_PATH ?=
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# FPGA target frequency. Should be in sync with the clock frequency
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# given by the parameters to the PLL in rtl/clk_reset_gen.v
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TARGET_FREQ ?= 24
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TARGET_FREQ ?= 21
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# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
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# bits wide; an EBR is 128 32-bits words)
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@ -76,13 +76,13 @@ module clk_reset_gen #(
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//
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// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
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//
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// Given the 12 MHz HFOSC clock set above, we get a final 24 MHz:
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// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
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//
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// (12000000 * (63 + 1)) / (2^5 * (0 + 1)) = 24000000
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// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'd0), // DIVR = 0
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.DIVF(7'd63), // DIVF = 63
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.DIVF(7'd55), // DIVF = 55
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.DIVQ(3'd5), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) pll_inst (
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@ -82,10 +82,10 @@ module uart (
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// The default bit rate is based on target clock frequency
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// divided by the bit rate times in order to hit the
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// center of the bits. I.e.
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// Clock: 24 MHz, 500 kbps
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// Divisor = 24E6 / 500E3 = 48
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// Clock: 21 MHz, 500 kbps
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// Divisor = 21E6 / 500E3 = 42
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// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
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localparam DEFAULT_BIT_RATE = 16'd48;
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localparam DEFAULT_BIT_RATE = 16'd42;
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localparam DEFAULT_DATA_BITS = 4'h8;
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localparam DEFAULT_STOP_BITS = 2'h1;
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@ -315,8 +315,8 @@ int main(void)
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}
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puts("\r\nTesting timer... 3");
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// Matching clock at 24 MHz, giving us timer in seconds
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*timer_prescaler = 24 * 1000000;
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// Matching clock at 21 MHz, giving us timer in seconds
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*timer_prescaler = 21 * 1000000;
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// Test timer expiration after 1s
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*timer = 1;
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