From 0cc991fea2e00d01c5b7cf7bfa7e605c6cf02040 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mikael=20=C3=85gren?= <mikael@tillitis.se>
Date: Wed, 12 Feb 2025 15:30:04 +0100
Subject: [PATCH] PoC: fpga: Revert back to 21 MHz

To avoid having to find a new nextpnr seed, for small changes, during
development
---
 hw/application_fpga/Makefile                               | 2 +-
 hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v | 6 +++---
 hw/application_fpga/core/uart/rtl/uart.v                   | 6 +++---
 hw/application_fpga/fw/testfw/main.c                       | 4 ++--
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
index d33bbef..624a56f 100644
--- a/hw/application_fpga/Makefile
+++ b/hw/application_fpga/Makefile
@@ -28,7 +28,7 @@ ICESTORM_PATH ?=
 
 # FPGA target frequency. Should be in sync with the clock frequency
 # given by the parameters to the PLL in rtl/clk_reset_gen.v
-TARGET_FREQ ?= 24
+TARGET_FREQ ?= 21
 
 # Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
 # bits wide; an EBR is 128 32-bits words)
diff --git a/hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v b/hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
index 1a68b10..b3a0ce9 100644
--- a/hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
+++ b/hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
@@ -76,13 +76,13 @@ module clk_reset_gen #(
   //
   // F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
   //
-  // Given the 12 MHz HFOSC clock set above, we get a final 24 MHz:
+  // Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
   //
-  // (12000000 * (63 + 1)) / (2^5 * (0 + 1)) = 24000000
+  // (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
   SB_PLL40_CORE #(
       .FEEDBACK_PATH("SIMPLE"),
       .DIVR(4'd0),  // DIVR =  0
-      .DIVF(7'd63),  // DIVF = 63
+      .DIVF(7'd55),  // DIVF = 55
       .DIVQ(3'd5),  // DIVQ =  5
       .FILTER_RANGE(3'b001)  // FILTER_RANGE = 1
   ) pll_inst (
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
index c37f5c9..1d3a6b1 100644
--- a/hw/application_fpga/core/uart/rtl/uart.v
+++ b/hw/application_fpga/core/uart/rtl/uart.v
@@ -82,10 +82,10 @@ module uart (
   // The default bit rate is based on target clock frequency
   // divided by the bit rate times in order to hit the
   // center of the bits. I.e.
-  // Clock: 24 MHz, 500 kbps
-  // Divisor = 24E6 / 500E3 = 48
+  // Clock: 21 MHz, 500 kbps
+  // Divisor = 21E6 / 500E3 = 42
   // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
-  localparam DEFAULT_BIT_RATE = 16'd48;
+  localparam DEFAULT_BIT_RATE = 16'd42;
   localparam DEFAULT_DATA_BITS = 4'h8;
   localparam DEFAULT_STOP_BITS = 2'h1;
 
diff --git a/hw/application_fpga/fw/testfw/main.c b/hw/application_fpga/fw/testfw/main.c
index 362c053..7d65ddc 100644
--- a/hw/application_fpga/fw/testfw/main.c
+++ b/hw/application_fpga/fw/testfw/main.c
@@ -315,8 +315,8 @@ int main(void)
 	}
 
 	puts("\r\nTesting timer... 3");
-	// Matching clock at 24 MHz, giving us timer in seconds
-	*timer_prescaler = 24 * 1000000;
+	// Matching clock at 21 MHz, giving us timer in seconds
+	*timer_prescaler = 21 * 1000000;
 
 	// Test timer expiration after 1s
 	*timer = 1;