PoC: fpga: Revert back to 21 MHz

To avoid having to find a new nextpnr seed, for small changes, during
development
This commit is contained in:
Mikael Ågren 2025-02-12 15:30:04 +01:00
parent d65e1eec4e
commit 0cc991fea2
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4 changed files with 9 additions and 9 deletions

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@ -28,7 +28,7 @@ ICESTORM_PATH ?=
# FPGA target frequency. Should be in sync with the clock frequency # FPGA target frequency. Should be in sync with the clock frequency
# given by the parameters to the PLL in rtl/clk_reset_gen.v # given by the parameters to the PLL in rtl/clk_reset_gen.v
TARGET_FREQ ?= 24 TARGET_FREQ ?= 21
# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16 # Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
# bits wide; an EBR is 128 32-bits words) # bits wide; an EBR is 128 32-bits words)

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@ -76,13 +76,13 @@ module clk_reset_gen #(
// //
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1)) // F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
// //
// Given the 12 MHz HFOSC clock set above, we get a final 24 MHz: // Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
// //
// (12000000 * (63 + 1)) / (2^5 * (0 + 1)) = 24000000 // (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #( SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"), .FEEDBACK_PATH("SIMPLE"),
.DIVR(4'd0), // DIVR = 0 .DIVR(4'd0), // DIVR = 0
.DIVF(7'd63), // DIVF = 63 .DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5 .DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1 .FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst ( ) pll_inst (

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@ -82,10 +82,10 @@ module uart (
// The default bit rate is based on target clock frequency // The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the // divided by the bit rate times in order to hit the
// center of the bits. I.e. // center of the bits. I.e.
// Clock: 24 MHz, 500 kbps // Clock: 21 MHz, 500 kbps
// Divisor = 24E6 / 500E3 = 48 // Divisor = 21E6 / 500E3 = 42
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd48; localparam DEFAULT_BIT_RATE = 16'd42;
localparam DEFAULT_DATA_BITS = 4'h8; localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1; localparam DEFAULT_STOP_BITS = 2'h1;

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@ -315,8 +315,8 @@ int main(void)
} }
puts("\r\nTesting timer... 3"); puts("\r\nTesting timer... 3");
// Matching clock at 24 MHz, giving us timer in seconds // Matching clock at 21 MHz, giving us timer in seconds
*timer_prescaler = 24 * 1000000; *timer_prescaler = 21 * 1000000;
// Test timer expiration after 1s // Test timer expiration after 1s
*timer = 1; *timer = 1;