Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-11-25 18:06:35 -05:00
Code Issues Projects Releases Packages Wiki Activity

PoC: fpga: Revert back to 21 MHz

Browse source 
To avoid having to find a new nextpnr seed, for small changes, during
development
This commit is contained in:
Mikael Ågren 2025-02-12 15:30:04 +01:00
parent d65e1eec4e
commit 0cc991fea2
No known key found for this signature in database
GPG key ID: E02DA3D397792C46
4 changed files with 9 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/application_fpga/core/uart/rtl/uart.v
View file

@ -82,10 +82,10 @@ module uart (
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 24 MHz, 500 kbps
// Divisor = 24E6 / 500E3 = 48
// Clock: 21 MHz, 500 kbps
// Divisor = 21E6 / 500E3 = 42
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd48;
localparam DEFAULT_BIT_RATE = 16'd42;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;