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fpga: Format Verilog

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Michael Cardell Widerkrantz 2025-02-11 14:37:29 +01:00
parent aedd6102ea
commit 050e0f2673
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GPG key ID: D3DB3DDF57E704E5
4 changed files with 6 additions and 6 deletions
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2
hw/application_fpga/rtl/application_fpga.v
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@ -297,7 +297,7 @@ module application_fpga (
.txd(interface_rx), .txd(interface_rx),
.ch552_cts(interface_ch552_cts), .ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts), .fpga_cts (interface_fpga_cts),
.cs(uart_cs), .cs(uart_cs),
.we(uart_we), .we(uart_we),

2
hw/application_fpga/tb/application_fpga_sim.v
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@ -308,7 +308,7 @@ module application_fpga_sim (
.txd(interface_rx), .txd(interface_rx),
.ch552_cts(interface_ch552_cts), .ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts), .fpga_cts (interface_fpga_cts),
.cs(uart_cs), .cs(uart_cs),
.we(uart_we), .we(uart_we),