From 050e0f2673f4125f8932b2194a5cb8814cbb0976 Mon Sep 17 00:00:00 2001
From: Michael Cardell Widerkrantz <mc@tillitis.se>
Date: Tue, 11 Feb 2025 14:37:29 +0100
Subject: [PATCH] fpga: Format Verilog

---
 hw/application_fpga/core/uart/rtl/uart_core.v | 2 +-
 hw/application_fpga/core/uart/rtl/uart_fifo.v | 2 +-
 hw/application_fpga/rtl/application_fpga.v    | 6 +++---
 hw/application_fpga/tb/application_fpga_sim.v | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/application_fpga/core/uart/rtl/uart_core.v b/hw/application_fpga/core/uart/rtl/uart_core.v
index 95716ad..7a4dd61 100644
--- a/hw/application_fpga/core/uart/rtl/uart_core.v
+++ b/hw/application_fpga/core/uart/rtl/uart_core.v
@@ -360,7 +360,7 @@ module uart_core (
           // Just a glitch.
           rxd_bitrate_ctr_rst = 1;
           erx_ctrl_new = ERX_IDLE;
-          erx_ctrl_we  = 1;
+          erx_ctrl_we = 1;
         end
 
         else begin
diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v
index 3c2449a..0963796 100644
--- a/hw/application_fpga/core/uart/rtl/uart_fifo.v
+++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v
@@ -50,7 +50,7 @@ module uart_fifo (
     output wire [7 : 0] out_data,
     input  wire         out_ack,
 
-    output wire         fpga_cts
+    output wire fpga_cts
 );
 
 
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index 59428e3..4d86e10 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -20,8 +20,8 @@ module application_fpga (
     output wire interface_rx,
     input  wire interface_tx,
 
-    input  wire interface_ch552_cts, // CH552 clear to send,  1 = OK, 0 = NOK
-    output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
+    input  wire interface_ch552_cts,  // CH552 clear to send,  1 = OK, 0 = NOK
+    output wire interface_fpga_cts,   // FPGA clear to send, 1 = OK, 0 = NOK
 
     output wire spi_ss,
     output wire spi_sck,
@@ -297,7 +297,7 @@ module application_fpga (
       .txd(interface_rx),
 
       .ch552_cts(interface_ch552_cts),
-      .fpga_cts(interface_fpga_cts),
+      .fpga_cts (interface_fpga_cts),
 
       .cs(uart_cs),
       .we(uart_we),
diff --git a/hw/application_fpga/tb/application_fpga_sim.v b/hw/application_fpga/tb/application_fpga_sim.v
index 047e624..94e13ee 100644
--- a/hw/application_fpga/tb/application_fpga_sim.v
+++ b/hw/application_fpga/tb/application_fpga_sim.v
@@ -308,7 +308,7 @@ module application_fpga_sim (
       .txd(interface_rx),
 
       .ch552_cts(interface_ch552_cts),
-      .fpga_cts(interface_fpga_cts),
+      .fpga_cts (interface_fpga_cts),
 
       .cs(uart_cs),
       .we(uart_we),