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fpga: Format Verilog

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Michael Cardell Widerkrantz 2025-02-11 14:37:29 +01:00
parent aedd6102ea
commit 050e0f2673
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4 changed files with 6 additions and 6 deletions
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6
hw/application_fpga/rtl/application_fpga.v
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@ -20,8 +20,8 @@ module application_fpga (
output wire interface_rx,
input wire interface_tx,
input wire interface_ch552_cts, // CH552 clear to send, 1 = OK, 0 = NOK
output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
input wire interface_ch552_cts, // CH552 clear to send, 1 = OK, 0 = NOK
output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
output wire spi_ss,
output wire spi_sck,
@ -297,7 +297,7 @@ module application_fpga (
.txd(interface_rx),
.ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts),
.fpga_cts (interface_fpga_cts),
.cs(uart_cs),
.we(uart_we),