fpga: Format Verilog

hw/application_fpga/core/uart/rtl/uart_core.v

@@ -360,7 +360,7 @@ module uart_core (
           // Just a glitch.
           rxd_bitrate_ctr_rst = 1;
           erx_ctrl_new = ERX_IDLE;
-          erx_ctrl_we  = 1;
+          erx_ctrl_we = 1;
         end
 
         else begin

hw/application_fpga/core/uart/rtl/uart_fifo.v

@@ -50,7 +50,7 @@ module uart_fifo (
     output wire [7 : 0] out_data,
     input  wire         out_ack,
 
-    output wire         fpga_cts
+    output wire fpga_cts
 );