mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-09-09 03:02:42 +00:00
248 lines
6.8 KiB
Verilog
248 lines
6.8 KiB
Verilog
![]() |
//======================================================================
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//
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// tb_timer_core.v
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// --------------
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// Testbench for the timer core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module tb_timer_core();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 0;
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parameter DUMP_WAIT = 0;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_start;
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reg tb_stop;
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reg [31 : 0] tb_prescaler;
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reg [31 : 0] tb_timer;
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wire [31 : 0] tb_curr_prescaler;
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wire [31 : 0] tb_curr_timer;
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wire tb_ready;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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timer_core dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.prescaler_value(tb_prescaler),
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.timer_value(tb_timer),
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.start(tb_start),
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.stop(tb_stop),
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.curr_prescaler(tb_curr_prescaler),
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.curr_timer(tb_curr_timer),
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.ready(tb_ready)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (tb_monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin
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$display("State of DUT");
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$display("------------");
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$display("Cycle: %08d", cycle_ctr);
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$display("");
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$display("Inputs and outputs:");
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$display("start: 0x%1x, stop: 0x%1x, ready: 0x%1x",
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dut.start, dut.stop, dut.ready);
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$display("prescaler_value: 0x%08x, timer_value: 0x%08x",
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dut.prescaler_value, dut.timer_value);
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$display("");
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$display("Internal state:");
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$display("prescaler_reg: 0x%08x, prescaler_new: 0x%08x",
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dut.prescaler_reg, dut.prescaler_new);
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$display("prescaler_set: 0x%1x, prescaler_dec: 0x%1x",
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dut.prescaler_set, dut.prescaler_dec);
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$display("");
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$display("timer_reg: 0x%08x, timer_new: 0x%08x",
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dut.timer_reg, dut.timer_new);
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$display("timer_set: 0x%1x, timer_dec: 0x%1x",
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dut.timer_set, dut.timer_dec);
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$display("");
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$display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%1x",
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dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
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$display("");
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- DUT before reset:");
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dump_dut_state();
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$display("--- Toggling reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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$display("--- DUT after reset:");
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dump_dut_state();
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// wait_ready()
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//
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// Wait for the ready flag in the dut to be set.
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//
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// Note: It is the callers responsibility to call the function
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// when the dut is actively processing and will in fact at some
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// point set the flag.
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//----------------------------------------------------------------
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task wait_ready;
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begin
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#(2 * CLK_PERIOD);
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while (!tb_ready)
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begin
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#(CLK_PERIOD);
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if (DUMP_WAIT)
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begin
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dump_dut_state();
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end
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end
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end
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endtask // wait_ready
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_monitor = 0;
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tb_clk = 0;
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tb_reset_n = 1;
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tb_start = 1'h0;
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tb_stop = 1'h0;
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tb_prescaler = 32'h0;
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tb_timer = 32'h0;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// test()
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// Runs an encipher, decipher test with given key and plaintext
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// The generated ciphertext is verified with the given ciphertet.
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// The generated plaintxt is also verified against the
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// given plaintext.
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//----------------------------------------------------------------
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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tb_monitor = 1;
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$display("--- test1 started.");
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dump_dut_state();
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tb_prescaler = 32'h6;
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tb_timer = 32'h9;
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#(CLK_PERIOD);
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tb_start = 1'h1;
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#(CLK_PERIOD);
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tb_start = 1'h0;
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wait_ready();
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#(CLK_PERIOD);
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tb_monitor = 0;
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$display("--- test1 completed.");
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$display("");
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end
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endtask // test1
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//----------------------------------------------------------------
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// timer_core_test
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//
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// Test vectors from:
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//----------------------------------------------------------------
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initial
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begin : timer_core_test
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$display("--- Simulation of TIMER core started.");
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$display("");
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init_sim();
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reset_dut();
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test1();
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$display("");
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$display("--- Simulation of timer core completed.");
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$finish;
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end // timer_core_test
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endmodule // tb_timer_core
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//======================================================================
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// EOF tb_timer_core.v
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//======================================================================
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