portapack-mayhem/hardware/portapack_h1/audio.sch
Jared Boone e7c0fa394b PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.

* PCB: Move HackRF header P9 to B.CrtYd layer.

* PCB: Change a Tg reference I missed.

* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.

* PCB: Got cold feet, switched back to rectangular pads.

* PCB: Add Eco layers to be visible and Gerber output.

* PCB: Use aux origin for plotting, for tidier coordinates.

* PCB: Output Gerber job file, because why not?

* Schematic: Correct footprints for two reference-related components.

* Schematic: Remove manfuacturer and part number for DNP component.

* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.

* PCB: Update netlist and footprints from schematic.

* Netlist: Updated component values, footprints.

* PCB: Nudge some components and traces to address DRC clearance violations.

* PCB: Allow KiCad to update zone timestamps (again?!).

* PCB: Generate *all* Gerber layers.

* Schematic, PCB: Update revision to 20181025.

* PCB: Adjust fab layer annotations orientation and font size.

* PCB: Hide mounting hole reference designators on silk layer.

* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.

* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.

* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.

* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.

* PCB: Change solder mask color to blue.

* Schematic, PCB: Update revision to 20181029.

* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.

* Update schematic

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Clock Manager: Actually store chosen clock reference

Similarly-named local was covering a member and discarding the value.

* Clock Manager: Reference type which contains source, frequency.

* Setup: Display reference source, frequency in frequency correction screen.

* LPC43xx API: Add extern "C" for use from C++.

* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.

* I2S: Add BASE_AUDIO_CLK management.

* Add MOTOCON_PWM clock/reset structure.

* Serial: Fix dumb typos.

* Serial: Remove extra reference operator.

* Serial: Cut-and-paste error in structure type name.

* Move SCU structure from PAL to LPC43xx API.

It'd be nice if I gave some thought to where code should live before I commit it.

* VAA power: Move code to HackRF board file

It doesn't belong in PAL.

* MAX5 CPLD: Add SAMPLE and EXTEST methods.

* Flash image: Change packing scheme to use flash more efficiently.

Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).

* Clock Manager: Remove PLL1 power down function.

* Move and rename peripherals reset function to board module.

* Remove unused peripheral/clock management.

* Clock Manager: Extract switch to IRC into separate function.

* Clock Manager: More explicit shutdown of clocks, clock generator.

* Move initialization to board module.

* ChibiOS: Rename "application" board, add "baseband" board.

There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.

* Clock Manager: Remove unused crystal enable/disable code.

* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.

* Reset peripherals on app shutdown.

Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).

* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.

This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.

* Audio app: Stop audio PLL on shutdown.

* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.

This was changing the BASE_M4_CLK when a baseband was run.

* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.

* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.

* Consolidate hardware init code to some degree.

ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.

* Migrate some startup code to application board.

* Si5351: Use correct methods for reset().

update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.

* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.

* Change application board.c to .cpp, with required dependent changes

* Board: Clean up SCU configuration code/data.

* I2S: Add shutdown code and use it.

* LPC43xx: Consolidate a bunch of structures that had been scattered all over.

...because I'm an undisciplined coder.

* I2S: Fix ordering of branch and base clock disable.

Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.

* Controls: Save and expose raw navigation wheel switch state

I need to do some work on debouncing and ignoring simultaneous key presses.

* Controls: Add debug view for switches state.

* Controls: Ignore all key presses until all keys are released.

This should address some mechanical quirks of the navigation wheel used on the PortaPack.

* Clock Manager: Wait for only the necessary PLL to lock.

Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...

* CMake: Pull HackRF project from GitHub and build.

* CMake: Remove commented code.

* CMake: Clone HackRF via HTTPS, not SSH.

* CMake: Extra pause for slow post-DFU firmware boot-up.

* CMake: TODO to fix SVF/XSVF file source.

* CMake: Ask HackRF hackrf_usb to make DFU binary.

* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.

* Travis-CI: Update build environment to Ubuntu xenial

Previously Trusty.

* Travis-CI: Incorrectly structured my request for dfu-util package.

I'm soooo talented.

* ldscript: Mark flash, ram with correct R/W/X flags.

* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.

* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.

* Documentation: Update product photos and README.

* Documentation: Add TCXO feature to README description.

* Application: Rearrange files to match HAVOC directory structure.

* Map view in AIS (#213)

* Added GeoMapView to AISRecentEntryDetailView

* Added autoupdate in AIS map

* Revert "Map view in AIS (#213)"

This reverts commit 262c030224.

This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.

* Revert "Upstream merge to make new revision of PortaPack work (#206)"

This reverts commit 920b98f7c9.

This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.

* CPLD: Pull bitstream from HackRF project.

* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.

* CPLD: Don't load HackRF CPLD bitstream into RAM.

Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.

* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.

* PinConfig: Drive CPLD pins correctly.

* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.

* CMake: Fix HackRF CPLD SVF dependency.

Build would break on the first pass, but work if you restarted make.

* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree

* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.

* CMake: Choose a CMP0005 policy to quiet CMake warnings.

* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.

* Radio Settings: Change reference clock text color.

Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 18:25:11 +00:00

912 lines
21 KiB
Plaintext

EESchema Schematic File Version 4
LIBS:portapack_h1-cache
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Title "PortaPack H1"
Date "2018-10-29"
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Comment2 "License: GNU General Public License, version 2"
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F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 4900 7200 60 0001 C CNN
F 3 "" H 4900 7200 60 0000 C CNN
F 4 "Murata" H 4900 7200 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 4900 7200 60 0001 C CNN "Part"
F 6 "DNP" H 5000 7100 50 0000 C CNN "DNP"
1 4900 7200
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR010
U 1 1 53A8C726
P 1600 7500
F 0 "#PWR010" H 1600 7500 30 0001 C CNN
F 1 "GND" H 1600 7430 30 0001 C CNN
F 2 "" H 1600 7500 60 0000 C CNN
F 3 "" H 1600 7500 60 0000 C CNN
1 1600 7500
1 0 0 -1
$EndComp
$Comp
L Device:C C11
U 1 1 53A8C72C
P 3800 7200
F 0 "C11" H 3850 7300 50 0000 L CNN
F 1 "10U" H 3850 7100 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 3800 7200 60 0001 C CNN
F 3 "" H 3800 7200 60 0000 C CNN
F 4 "Murata" H 3800 7200 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 3800 7200 60 0001 C CNN "Part"
1 3800 7200
-1 0 0 -1
$EndComp
Text Notes 2300 2500 0 60 ~ 0
I2C Addresses on HackRF I2C bus (I2C0?):\n\n0b1100000: Si5351C-B\n0b0010010: AK4951 audio codec
Text HLabel 5800 4100 2 60 Input ~ 0
SCL
Text HLabel 5800 4000 2 60 BiDi ~ 0
SDA
Text HLabel 7200 3800 2 60 Output ~ 0
SDTO
NoConn ~ 10300 2200
NoConn ~ 10300 2300
Text HLabel 7200 3700 2 60 BiDi ~ 0
LRCK
Text HLabel 5800 3500 2 60 Input ~ 0
MCKI
Text HLabel 5800 3900 2 60 Input ~ 0
SDTI
Text HLabel 7200 3600 2 60 BiDi ~ 0
BICK
$Comp
L power:GND #PWR011
U 1 1 58AF7E95
P 2700 3800
F 0 "#PWR011" H 2700 3800 30 0001 C CNN
F 1 "GND" H 2700 3730 30 0001 C CNN
F 2 "" H 2700 3800 60 0000 C CNN
F 3 "" H 2700 3800 60 0000 C CNN
1 2700 3800
0 1 1 0
$EndComp
$Comp
L power:GND #PWR012
U 1 1 58AF81BD
P 5200 2800
F 0 "#PWR012" H 5200 2800 30 0001 C CNN
F 1 "GND" H 5200 2730 30 0001 C CNN
F 2 "" H 5200 2800 60 0000 C CNN
F 3 "" H 5200 2800 60 0000 C CNN
1 5200 2800
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR013
U 1 1 58AF82A8
P 3800 3400
F 0 "#PWR013" H 3800 3400 30 0001 C CNN
F 1 "GND" H 3800 3330 30 0001 C CNN
F 2 "" H 3800 3400 60 0000 C CNN
F 3 "" H 3800 3400 60 0000 C CNN
1 3800 3400
0 1 1 0
$EndComp
$Comp
L asahi_kasei:AK4951EN U1
U 1 1 58CC98F8
P 4850 3750
F 0 "U1" V 4950 3750 60 0000 C CNN
F 1 "AK4951EN" V 4850 3750 60 0000 C CNN
F 2 "ipc_qfn:IPC_QFN33P40_400X400X80L35X20T280N" V 4850 3750 60 0001 C CNN
F 3 "http://www.akm.com/akm/en/file/datasheet/AK4951EN.pdf" V 4850 3750 60 0001 C CNN
F 4 "Asahi Kasei" V 4850 3750 60 0001 C CNN "Mfr"
F 5 "AK4951EN" V 4850 3750 60 0001 C CNN "Part"
1 4850 3750
0 -1 -1 0
$EndComp
Text HLabel 5100 2800 1 60 Input ~ 0
SVDD
Text HLabel 3900 3700 0 60 Input ~ 0
AVDD
Text HLabel 4800 2800 1 60 Input ~ 0
DVDD
Text HLabel 5800 3400 2 60 Input ~ 0
TVDD
Text HLabel 4300 6900 0 60 Input ~ 0
SVDD
Text HLabel 3200 6900 0 60 Input ~ 0
AVDD
Text HLabel 2100 6900 0 60 Input ~ 0
DVDD
Text HLabel 1000 6900 0 60 Input ~ 0
TVDD
Text Label 3600 3900 0 60 ~ 0
VCOM
Text Label 3600 4000 0 60 ~ 0
REGFIL
Text Label 4300 2600 0 60 ~ 0
VEE
Text Label 3300 3500 0 60 ~ 0
CP
Text Label 3300 3600 0 60 ~ 0
CN
Text HLabel 7200 3900 2 60 Input ~ 0
PDN#
$Comp
L Device:R R2
U 1 1 58CF5E5F
P 5400 5050
F 0 "R2" V 5480 5050 50 0000 C CNN
F 1 "10K" V 5400 5050 50 0001 C CNN
F 2 "ipc_resc:IPC_RESC160X80X55L25N" H 5400 5050 60 0001 C CNN
F 3 "" H 5400 5050 60 0000 C CNN
F 4 "Yageo" V 5400 5050 60 0001 C CNN "Mfr"
F 5 "DNP" V 5400 5050 50 0000 C CNN "DNP"
1 5400 5050
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR014
U 1 1 58CF6206
P 5400 5400
F 0 "#PWR014" H 5400 5400 30 0001 C CNN
F 1 "GND" H 5400 5330 30 0001 C CNN
F 2 "" H 5400 5400 60 0000 C CNN
F 3 "" H 5400 5400 60 0000 C CNN
1 5400 5400
1 0 0 -1
$EndComp
Text Notes 8800 5700 0 60 ~ 0
PDN/SCL/SDA/SDTI/LRCK/BICK/MCKI:\n L: < 0.3 TVDD, H > 0.7 TVDD
Text Notes 8800 6000 0 60 ~ 0
Init: power down, EXT slave, PLL off\nBICK, LRCK: inputs
Text Notes 8800 6200 0 60 ~ 0
Input float OK: [LR]IN[123]
$Comp
L power:GND #PWR015
U 1 1 58D2C845
P 3900 4300
F 0 "#PWR015" H 3900 4300 30 0001 C CNN
F 1 "GND" H 3900 4230 30 0001 C CNN
F 2 "" H 3900 4300 60 0000 C CNN
F 3 "" H 3900 4300 60 0000 C CNN
1 3900 4300
0 1 1 0
$EndComp
$Comp
L esd:NUF4220MN U5
U 1 1 58D9A047
P 9700 3250
F 0 "U5" H 9400 3550 60 0000 L CNN
F 1 "NUF4220MN" H 9800 2950 60 0000 L CNN
F 2 "ipc_son:IPC_SON9P50_200X200X100L30X25T80X120N" H 9700 3250 60 0001 C CNN
F 3 "http://www.onsemi.com/pub/Collateral/NUF4220MN-D.PDF" H 9700 3250 60 0001 C CNN
F 4 "ON Semiconductor" H 9700 3250 60 0001 C CNN "Mfr"
F 5 "NUF4220MNT1G" H 9700 3250 60 0001 C CNN "Part"
1 9700 3250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR016
U 1 1 53A8C2CC
P 9700 3800
F 0 "#PWR016" H 9700 3800 30 0001 C CNN
F 1 "GND" H 9700 3730 30 0001 C CNN
F 2 "" H 9700 3800 60 0000 C CNN
F 3 "" H 9700 3800 60 0000 C CNN
1 9700 3800
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR017
U 1 1 58D9A87F
P 9100 3200
F 0 "#PWR017" H 9100 3200 30 0001 C CNN
F 1 "GND" H 9100 3130 30 0001 C CNN
F 2 "" H 9100 3200 60 0000 C CNN
F 3 "" H 9100 3200 60 0000 C CNN
1 9100 3200
0 1 1 0
$EndComp
Text Label 9600 2200 0 60 ~ 0
LHPOUT_X
Text Label 9600 2100 0 60 ~ 0
RHPOUT_X
Text Label 9600 2000 0 60 ~ 0
GND_X
Text Label 9600 1900 0 60 ~ 0
MIC_X
Text Label 4900 6400 0 60 ~ 0
MIC
Text Label 10300 3100 0 60 ~ 0
LHPOUT_X
Text Label 10300 3300 0 60 ~ 0
MIC_X
Text Label 10300 3200 0 60 ~ 0
GND_X
Text Label 10300 3400 0 60 ~ 0
RHPOUT_X
Text Label 8700 3100 0 60 ~ 0
LHPOUT
Text Label 8700 3400 0 60 ~ 0
RHPOUT
Text Label 8700 3300 0 60 ~ 0
MIC
$Comp
L tp:TP TP1
U 1 1 58EDDA01
P 3700 4800
F 0 "TP1" H 3500 4800 60 0000 C CNN
F 1 "TP" H 3650 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 3700 4800 60 0001 C CNN
F 3 "" H 3700 4800 60 0001 C CNN
1 3700 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP2
U 1 1 58EDDAEE
P 4500 4800
F 0 "TP2" H 4300 4800 60 0000 C CNN
F 1 "TP" H 4450 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 4500 4800 60 0001 C CNN
F 3 "" H 4500 4800 60 0001 C CNN
1 4500 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP3
U 1 1 58EDDB69
P 4600 4800
F 0 "TP3" H 4400 4800 60 0000 C CNN
F 1 "TP" H 4550 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 4600 4800 60 0001 C CNN
F 3 "" H 4600 4800 60 0001 C CNN
1 4600 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP4
U 1 1 58EDDC3F
P 4900 4800
F 0 "TP4" H 4700 4800 60 0000 C CNN
F 1 "TP" H 4850 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 4900 4800 60 0001 C CNN
F 3 "" H 4900 4800 60 0001 C CNN
1 4900 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP5
U 1 1 58EDDCA8
P 5000 4800
F 0 "TP5" H 4800 4800 60 0000 C CNN
F 1 "TP" H 4950 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 5000 4800 60 0001 C CNN
F 3 "" H 5000 4800 60 0001 C CNN
1 5000 4800
0 -1 -1 0
$EndComp
$Comp
L tp:TP TP6
U 1 1 58EDDD10
P 5100 4800
F 0 "TP6" H 4900 4800 60 0000 C CNN
F 1 "TP" H 5050 4650 60 0001 C CNN
F 2 "tp:TP_1MM" H 5100 4800 60 0001 C CNN
F 3 "" H 5100 4800 60 0001 C CNN
1 5100 4800
0 -1 -1 0
$EndComp
$Comp
L header:HEADER_1X3 J1
U 1 1 58F82DA0
P 5800 2100
F 0 "J1" H 5800 1850 60 0000 C CNN
F 1 "HEADER_1X3" H 5800 1850 60 0001 C CNN
F 2 "jst:JST_S3B-PH-SM4-TB" H 5800 1900 60 0001 C CNN
F 3 "http://www.jst-mfg.com/product/pdf/eng/ePH.pdf" H 5800 1900 60 0001 C CNN
F 4 "JST" H 5800 2100 60 0001 C CNN "Mfr"
F 5 "S3B-PH-SM4-TB" H 5800 2100 60 0001 C CNN "Part"
F 6 "DNP" H 5800 2100 60 0000 C CNN "DNP"
1 5800 2100
1 0 0 1
$EndComp
$Comp
L power:GND #PWR018
U 1 1 58F8315C
P 5400 2100
F 0 "#PWR018" H 5400 2100 30 0001 C CNN
F 1 "GND" H 5400 2030 30 0001 C CNN
F 2 "" H 5400 2100 60 0000 C CNN
F 3 "" H 5400 2100 60 0000 C CNN
1 5400 2100
0 1 1 0
$EndComp
Wire Wire Line
9000 1900 10300 1900
Wire Wire Line
4600 1500 6400 1500
Wire Wire Line
4700 1600 6800 1600
Connection ~ 6400 1500
Wire Wire Line
5200 2900 5200 2800
Wire Wire Line
3800 3400 3900 3400
Wire Wire Line
2700 3800 2800 3800
Wire Wire Line
5700 3400 5800 3400
Wire Wire Line
5100 2900 5100 2800
Wire Wire Line
3900 3700 4000 3700
Wire Wire Line
4800 2900 4800 2800
Wire Wire Line
1000 6900 1200 6900
Connection ~ 1200 6900
Wire Wire Line
3200 6900 3400 6900
Connection ~ 3400 6900
Wire Wire Line
4300 6900 4500 6900
Connection ~ 4500 6900
Wire Wire Line
4500 2600 4500 2900
Wire Wire Line
3900 2600 4500 2600
Wire Wire Line
4000 3500 3100 3500
Wire Wire Line
3100 3500 3100 3000
Wire Wire Line
3100 3000 2800 3000
Wire Wire Line
2800 3600 4000 3600
Wire Wire Line
5700 4000 5800 4000
Wire Wire Line
5800 4100 5700 4100
Wire Wire Line
4700 2900 4700 1600
Wire Wire Line
4600 1500 4600 2900
Wire Wire Line
5700 3900 5800 3900
Wire Wire Line
5700 3800 6700 3800
Wire Wire Line
5700 3700 6700 3700
Wire Wire Line
5700 3600 6700 3600
Wire Wire Line
5700 3500 5800 3500
Wire Wire Line
5200 4600 5200 4700
Wire Wire Line
5200 4700 5400 4700
Wire Wire Line
4800 5300 4800 4600
Wire Wire Line
5000 6000 4700 6000
Connection ~ 4700 6000
Connection ~ 5400 4700
Wire Wire Line
4700 6400 5200 6400
Wire Wire Line
4000 4300 3900 4300
Wire Wire Line
9000 2000 10300 2000
Wire Wire Line
9200 3200 9100 3200
Wire Wire Line
9700 3800 9700 3700
Wire Wire Line
9000 2100 10300 2100
Wire Wire Line
5000 5300 4800 5300
Connection ~ 6800 1600
Wire Wire Line
9000 2200 10100 2200
Wire Wire Line
10100 2200 10100 2400
Wire Wire Line
10100 2400 10300 2400
Wire Wire Line
10900 3100 10200 3100
Wire Wire Line
10900 3200 10200 3200
Wire Wire Line
10900 3300 10200 3300
Wire Wire Line
10900 3400 10200 3400
Wire Wire Line
8600 3400 9200 3400
Wire Wire Line
8600 3300 9200 3300
Wire Wire Line
8600 3100 9200 3100
Wire Wire Line
4500 4700 4500 4600
Wire Wire Line
4600 4700 4600 4600
Wire Wire Line
4900 4700 4900 4600
Wire Wire Line
5000 4700 5000 4600
Wire Wire Line
5100 4700 5100 4600
Wire Wire Line
3700 4100 4000 4100
Connection ~ 3900 3400
Wire Wire Line
3700 4100 3700 4700
Wire Wire Line
4000 4000 3500 4000
Wire Wire Line
3500 4000 3500 4300
Wire Wire Line
4000 3900 3400 3900
Wire Wire Line
3400 3900 3400 4000
Wire Wire Line
2800 3800 2800 4000
Connection ~ 2800 3800
Connection ~ 2800 4000
Wire Wire Line
5500 2000 4900 2000
Wire Wire Line
4900 2000 4900 2900
Wire Wire Line
5500 2200 5000 2200
Wire Wire Line
5000 2200 5000 2900
Wire Wire Line
5500 2100 5400 2100
$Comp
L passive:RPACK4 RP1
U 1 1 58F9564A
P 6900 3750
F 0 "RP1" H 6900 4000 60 0000 C CNN
F 1 "220R" H 6900 3500 60 0000 C CNN
F 2 "ipc_rescax:IPC_RESCAXS8P80_320X160X60L30X45N" H 6900 3750 60 0001 C CNN
F 3 "https://industrial.panasonic.com/cdbs/www-data/pdf/AOC0000/AOC0000C14.pdf" H 6900 3750 60 0001 C CNN
F 4 "Panasonic" H 6900 3750 60 0001 C CNN "Mfr"
F 5 "EXB-38V221JV" H 6900 3750 60 0001 C CNN "Part"
1 6900 3750
1 0 0 -1
$EndComp
Wire Wire Line
6700 3900 6600 3900
Wire Wire Line
6600 3900 6600 4700
Wire Wire Line
7100 3600 7200 3600
Wire Wire Line
7200 3700 7100 3700
Wire Wire Line
7100 3800 7200 3800
Wire Wire Line
7200 3900 7100 3900
Text Label 6200 3600 0 60 ~ 0
BICK_R
Text Label 6200 3700 0 60 ~ 0
LRCK_R
Text Label 6200 3800 0 60 ~ 0
SDTO_R
Text Label 5600 4700 0 60 ~ 0
PDN#_R
Text Label 5100 2000 0 60 ~ 0
SPP
Text Label 5100 2200 0 60 ~ 0
SPN
Wire Wire Line
2100 6900 2300 6900
Text Notes 1800 7700 0 60 ~ 0
No 10U on DVDD, very near regulator 10U.
Text Notes 4250 7700 0 60 ~ 0
No 10U on SVDD to comply with USB inrush spec.
Wire Wire Line
6400 1500 7600 1500
Wire Wire Line
1200 6900 1600 6900
Wire Wire Line
3400 6900 3800 6900
Wire Wire Line
4500 6900 4900 6900
Wire Wire Line
4700 6000 4700 6400
Wire Wire Line
5400 4700 6600 4700
Wire Wire Line
6800 1600 7600 1600
Wire Wire Line
3900 3400 4000 3400
Wire Wire Line
2800 3800 4000 3800
Wire Wire Line
2800 4000 2800 4300
Wire Wire Line
3900 2600 3900 2950
Wire Wire Line
3900 3250 3900 3400
Wire Wire Line
2800 3000 2800 3150
Wire Wire Line
2800 3600 2800 3450
Wire Wire Line
2800 4000 2950 4000
Wire Wire Line
2800 4300 2950 4300
Wire Wire Line
3250 4300 3500 4300
Wire Wire Line
3250 4000 3400 4000
Wire Wire Line
4700 4600 4700 5450
Wire Wire Line
4700 5750 4700 6000
Wire Wire Line
5000 5300 5000 5500
Wire Wire Line
5000 5800 5000 6000
Wire Wire Line
5400 5200 5400 5400
Wire Wire Line
5400 4700 5400 4900
Wire Wire Line
6400 2550 6400 2750
Wire Wire Line
6400 2000 6400 2250
Wire Wire Line
6400 1500 6400 1700
Wire Wire Line
6800 1600 6800 1700
Wire Wire Line
6800 2000 6800 2250
Wire Wire Line
6800 2550 6800 2750
Wire Wire Line
1200 6900 1200 7050
Wire Wire Line
1200 7350 1200 7500
Wire Wire Line
1600 7350 1600 7500
Wire Wire Line
1600 6900 1600 7050
Wire Wire Line
2300 6900 2300 7050
Wire Wire Line
2300 7350 2300 7500
Wire Wire Line
3400 7350 3400 7500
Wire Wire Line
3400 6900 3400 7050
Wire Wire Line
3800 6900 3800 7050
Wire Wire Line
3800 7350 3800 7500
Wire Wire Line
4500 7350 4500 7500
Wire Wire Line
4500 6900 4500 7050
Wire Wire Line
4900 6900 4900 7050
Wire Wire Line
4900 7350 4900 7500
$EndSCHEMATC