mirror of
https://github.com/eried/portapack-mayhem.git
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b8073bca0f
* Adding_TX_IQ_phase_Calibration_to_Mic_App * Adding_persistent_CAL_data_and_correct_init_data
381 lines
13 KiB
C++
381 lines
13 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "max2837.hpp"
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#include "hackrf_hal.hpp"
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#include "hackrf_gpio.hpp"
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using namespace hackrf::one;
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#include "ch.h"
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#include "hal.h"
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#include <algorithm>
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namespace max2837 {
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using namespace max283x;
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namespace lna {
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using namespace max283x::lna;
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constexpr std::array<uint8_t, 8> lookup_8db_steps{
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0b111, 0b011, 0b110, 0b010,
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0b100, 0b000, 0b000, 0b000};
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static uint_fast8_t gain_ordinal(const int8_t db) {
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const auto db_sat = gain_db_range.clip(db);
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return lna::lookup_8db_steps[(db_sat >> 3) & 7];
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}
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} /* namespace lna */
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namespace vga {
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using namespace max283x::vga;
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static uint_fast8_t gain_ordinal(const int8_t db) {
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const auto db_sat = gain_db_range.clip(db);
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return ((db_sat >> 1) & 0b11111) ^ 0b11111;
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}
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} /* namespace vga */
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namespace tx {
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using namespace max283x::tx;
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static uint_fast8_t gain_ordinal(const int8_t db) {
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const auto db_sat = gain_db_range.clip(db);
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uint8_t value = db_sat & 0x0f;
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value = (db_sat >= 16) ? (value | 0x20) : value;
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value = (db_sat >= 32) ? (value | 0x10) : value;
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return (value & 0b111111) ^ 0b111111;
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}
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} /* namespace tx */
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namespace filter {
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using namespace max283x::filter;
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static uint_fast8_t bandwidth_ordinal(const uint32_t bandwidth) {
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/* Determine filter setting that will provide bandwidth greater than or
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* equal to requested bandwidth.
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*/
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return std::lower_bound(bandwidths.cbegin(), bandwidths.cend(), bandwidth) - bandwidths.cbegin();
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}
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} /* namespace filter */
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/* Empirical testing indicates about 25us is necessary to get a valid
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* temperature sense conversion from the ADC.
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*/
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constexpr float seconds_for_temperature_sense_adc_conversion = 30.0e-6;
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constexpr halrtcnt_t ticks_for_temperature_sense_adc_conversion = (base_m4_clk_f * seconds_for_temperature_sense_adc_conversion + 1);
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constexpr uint32_t reference_frequency = max283x_reference_f;
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constexpr uint32_t pll_factor = 1.0 / (4.0 / 3.0 / reference_frequency) + 0.5;
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void MAX2837::init() {
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set_mode(Mode::Shutdown);
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gpio_max283x_enable.output();
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gpio_max2837_rxenable.output();
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gpio_max2837_txenable.output();
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_map.r.tx_gain.TXVGA_GAIN_SPI_EN = 1;
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_map.r.tx_gain.TXVGA_GAIN_MSB_SPI_EN = 1;
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_map.r.tx_gain.TXVGA_GAIN_SPI = 0x00;
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_map.r.lpf_3_vga_1.VGAMUX_enable = 1;
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_map.r.lpf_3_vga_1.VGA_EN = 1;
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_map.r.hpfsm_3.HPC_STOP = 1; /* 1kHz */
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_map.r.rx_top_rx_bias.LNAgain_SPI_EN = 1; /* control LNA gain from SPI */
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_map.r.rxrf_2.L = 0b000;
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_map.r.rx_top_rx_bias.VGAgain_SPI_EN = 1; /* control VGA gain from SPI */
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_map.r.vga_2.VGA = 0b01010;
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_map.r.lpf_3_vga_1.BUFF_VCM = 0b00; /* TODO: Check values out of ADC */
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_map.r.lpf_1.LPF_EN = 1; /* Enable low-pass filter */
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_map.r.lpf_1.ModeCtrl = 0b01; /* Rx LPF */
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_map.r.lpf_1.FT = 0b0000; /* 1,75MHz LPF */
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_map.r.spi_en.EN_SPI = 1; /* enable chip functions when ENABLE pin set */
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_map.r.lo_gen.LOGEN_2GM = 0;
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#if 0
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_map.r.rxrf_1.LNA_EN = 1;
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_map.r.rxrf_1.Mixer_EN = 1;
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_map.r.rxrf_1.RxLO_EN = 1;
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_map.r.rx_top.DOUT_DRVH = 0; /* slow down DOUT edges */
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_map.r.hpfsm_4.DOUT_CSB_SEL = 0; /* DOUT not tri-stated, is independent of CSB */
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_map.r.xtal_cfg.XTAL_CLKOUT_EN = 0; /* CLKOUT pin disabled. (Seems to have no effect.) */
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#endif
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_map.r.vga_3_rx_top.RSSI_EN_SPIenables = 1;
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_map.r.vga_3_rx_top.RSSI_MODE = 1; /* RSSI independent of RXHP */
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_dirty.set();
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flush();
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set_mode(Mode::Standby);
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}
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void MAX2837::set_tx_LO_iq_phase_calibration(const size_t v) {
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/* IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
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// TX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,0,1 (5dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
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set_mode(Mode::Tx_Calibration); // write to ram 3 LOGIC Pins .
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gpio_max283x_enable.output();
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gpio_max2837_rxenable.output();
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gpio_max2837_txenable.output();
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_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
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_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
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flush_one(Register::SPI_EN);
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_map.r.tx_lo_iq.TXLO_IQ_SPI_EN = 1; // reg 30 D5, TX LO I/Q Phase SPI Adjust. Active when Address 30 D5 (TXLO_IQ_SPI_EN) = 1.
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_map.r.tx_lo_iq.TXLO_IQ_SPI = v; // reg 30 D4:D0, TX LO I/Q Phase SPI Adjust.
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flush_one(Register::TX_LO_IQ);
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// Exit Calibration mode, Go back to reg 16, D1:D0 , Out of CALIBRATION , back to default conditions, but keep CS activated.
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_map.r.spi_en.CAL_SPI = 0; // Register Settings reg address 16, D1 (0 = Normal operation (default)
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_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (1 = Chip select enable )
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flush_one(Register::SPI_EN);
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set_mode(Mode::Standby); // Back 3 logic pins CALIBRATION mode -> Standby.
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}
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enum class Mask { // There are class Mask ,and class mode with same names, but they are not same.
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Enable = 0b001,
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RxEnable = 0b010,
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TxEnable = 0b100,
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Shutdown = 0b000,
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Standby = Enable,
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Receive = Enable | RxEnable,
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Transmit = Enable | TxEnable,
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Rx_calibration = Enable | RxEnable, // sets the same 3 x logic pins to the Receive operating mode.
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Tx_calibration = Enable | TxEnable, // sets the same 3 x logic pins to the Transmit operating mode.
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};
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Mask mode_mask(const Mode mode) { // based on enum Mode cases, we set up the correct 3 logic PINS .
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switch (mode) {
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case Mode::Standby:
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return Mask::Standby;
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case Mode::Receive:
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return Mask::Receive;
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case Mode::Transmit:
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return Mask::Transmit;
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case Mode::Rx_Calibration: // Let's add those two CAL logic pin settings- Rx and Tx calibration modes.
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return Mask::Rx_calibration; // same logic pins as Receive mode = Enable | RxEnable, (the difference is in Reg add 16 D1:DO)
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case Mode::Tx_Calibration: // Let's add this CAL Tx calibration mode = Transmit.
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return Mask::Tx_calibration; // same logic pins as Transmit = Enable | TxEnable,(the difference is in Reg add 16 D1:DO)
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default:
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return Mask::Shutdown;
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}
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}
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void MAX2837::set_mode(const Mode mode) { // We set up the 3 Logic Pins ENABLE, RXENABLE, TXENABLE accordingly to the max2837 mode case, that we want to set up .
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Mask mask = mode_mask(mode);
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gpio_max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
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gpio_max2837_rxenable.write(toUType(mask) & toUType(Mask::RxEnable));
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gpio_max2837_txenable.write(toUType(mask) & toUType(Mask::TxEnable));
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}
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void MAX2837::flush() {
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if (_dirty) {
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for (size_t n = 0; n < reg_count; n++) {
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if (_dirty[n]) {
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write(n, _map.w[n]);
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}
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}
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_dirty.clear();
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}
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}
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void MAX2837::flush_one(const Register reg) {
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const auto reg_num = toUType(reg);
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write(reg_num, _map.w[reg_num]);
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_dirty.clear(reg_num);
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}
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void MAX2837::write(const address_t reg_num, const reg_t value) {
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uint16_t t = (0U << 15) | (reg_num << 10) | (value & 0x3ffU);
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_target.transfer(&t, 1);
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}
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reg_t MAX2837::read(const address_t reg_num) {
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uint16_t t = (1U << 15) | (reg_num << 10);
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_target.transfer(&t, 1U);
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return t & 0x3ffU;
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}
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void MAX2837::write(const Register reg, const reg_t value) {
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write(toUType(reg), value);
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}
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reg_t MAX2837::read(const Register reg) {
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return read(toUType(reg));
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}
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void MAX2837::set_tx_vga_gain(const int_fast8_t db) {
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_map.r.tx_gain.TXVGA_GAIN_SPI = tx::gain_ordinal(db);
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_dirty[Register::TX_GAIN] = 1;
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flush();
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}
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void MAX2837::set_lna_gain(const int_fast8_t db) {
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_map.r.rxrf_2.L = lna::gain_ordinal(db);
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_dirty[Register::RXRF_2] = 1;
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flush();
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}
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void MAX2837::set_vga_gain(const int_fast8_t db) {
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_map.r.vga_2.VGA = vga::gain_ordinal(db);
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_dirty[Register::VGA_2] = 1;
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flush();
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}
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void MAX2837::set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) {
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_map.r.lpf_1.ModeCtrl = 0b01; /* Address reg 2, D3-D2, Set mode lowpass filter block to Rx LPF . Active when Address 6 D<9> = 1 */
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_map.r.lpf_1.FT = filter::bandwidth_ordinal(bandwidth_minimum);
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flush_one(Register::LPF_1);
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_map.r.vga_3_rx_top.LPF_MODE_SEL = 1; /* Address 6 reg, D9 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 2 D3:D2*/
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flush_one(Register::VGA_3_RX_TOP);
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_map.r.vga_3_rx_top.LPF_MODE_SEL = 0; /* Leave LPF_MODE_SEL 0 = Normal operation */
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flush_one(Register::VGA_3_RX_TOP);
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}
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void MAX2837::set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) {
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_map.r.lpf_1.ModeCtrl = 0b10; /* Address 2 reg, D3-D2, Set mode lowpass filter block to Tx LPF . Active when Address 6 D<9> = 1 */
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_map.r.lpf_1.FT = filter::bandwidth_ordinal(bandwidth_minimum);
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flush_one(Register::LPF_1);
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_map.r.vga_3_rx_top.LPF_MODE_SEL = 1; /* Address 6 reg, D9 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 2 D3:D2*/
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flush_one(Register::VGA_3_RX_TOP);
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_map.r.vga_3_rx_top.LPF_MODE_SEL = 0; /* Leave LPF_MODE_SEL 0 = Normal operation */
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flush_one(Register::VGA_3_RX_TOP);
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}
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bool MAX2837::set_frequency(const rf::Frequency lo_frequency) {
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/* TODO: This is a sad implementation. Refactor. */
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if (lo::band[0].contains(lo_frequency)) {
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_map.r.syn_int_div.LOGEN_BSW = 0b00; /* 2300 - 2399.99MHz */
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_map.r.rxrf_1.LNAband = 0; /* 2.3 - 2.5GHz */
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} else if (lo::band[1].contains(lo_frequency)) {
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_map.r.syn_int_div.LOGEN_BSW = 0b01; /* 2400 - 2499.99MHz */
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_map.r.rxrf_1.LNAband = 0; /* 2.3 - 2.5GHz */
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} else if (lo::band[2].contains(lo_frequency)) {
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_map.r.syn_int_div.LOGEN_BSW = 0b10; /* 2500 - 2599.99MHz */
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_map.r.rxrf_1.LNAband = 1; /* 2.5 - 2.7GHz */
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} else if (lo::band[3].contains(lo_frequency)) {
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_map.r.syn_int_div.LOGEN_BSW = 0b11; /* 2600 - 2700Hz */
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_map.r.rxrf_1.LNAband = 1; /* 2.5 - 2.7GHz */
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} else {
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return false;
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}
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_dirty[Register::SYN_INT_DIV] = 1;
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_dirty[Register::RXRF_1] = 1;
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const uint64_t div_q20 = (lo_frequency * (1 << 20)) / pll_factor;
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_map.r.syn_int_div.SYN_INTDIV = div_q20 >> 20;
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_dirty[Register::SYN_INT_DIV] = 1;
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_map.r.syn_fr_div_2.SYN_FRDIV_19_10 = (div_q20 >> 10) & 0x3ff;
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_dirty[Register::SYN_FR_DIV_2] = 1;
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/* flush to commit high FRDIV first, as low FRDIV commits the change */
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flush();
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_map.r.syn_fr_div_1.SYN_FRDIV_9_0 = (div_q20 & 0x3ff);
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_dirty[Register::SYN_FR_DIV_1] = 1;
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flush();
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return true;
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}
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void MAX2837::set_rx_lo_iq_calibration(const size_t v) {
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_map.r.rx_top_rx_bias.RX_IQERR_SPI_EN = 1;
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_dirty[Register::RX_TOP_RX_BIAS] = 1;
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_map.r.rxrf_2.iqerr_trim = v;
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_dirty[Register::RXRF_2] = 1;
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flush();
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}
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void MAX2837::set_rx_bias_trim(const size_t v) {
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_map.r.rx_top_rx_bias.EN_Bias_Trim = 1;
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_map.r.rx_top_rx_bias.BIAS_TRIM_SPI = v;
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_dirty[Register::RX_TOP_RX_BIAS] = 1;
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flush();
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}
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void MAX2837::set_vco_bias(const size_t v) {
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_map.r.vco_cfg.VCO_BIAS_SPI_EN = 1;
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_map.r.vco_cfg.VCO_BIAS_SPI = v;
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_dirty[Register::VCO_CFG] = 1;
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flush();
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}
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void MAX2837::set_rx_buff_vcm(const size_t v) {
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_map.r.lpf_3_vga_1.BUFF_VCM = v;
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_dirty[Register::LPF_3_VGA_1] = 1;
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flush();
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}
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int8_t MAX2837::temp_sense() {
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if (!_map.r.rx_top.ts_en) {
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_map.r.rx_top.ts_en = 1;
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flush_one(Register::RX_TOP);
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chThdSleepMilliseconds(1);
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}
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_map.r.rx_top.ts_adc_trigger = 1;
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flush_one(Register::RX_TOP);
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halPolledDelay(ticks_for_temperature_sense_adc_conversion);
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/*
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* Conversion to degrees C determined by testing - does not match data sheet.
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*/
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reg_t value = read(Register::TEMP_SENSE) & 0x1F;
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_map.r.rx_top.ts_adc_trigger = 0;
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flush_one(Register::RX_TOP);
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return std::min(127, (int)(value * 4.31 - 40)); // reg value is 0 to 31; possible return range is -40 C to 127 C
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}
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} // namespace max2837
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