mirror of
https://github.com/eried/portapack-mayhem.git
synced 2024-09-20 08:05:44 +00:00
e7c0fa394b
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric. * PCB: Move HackRF header P9 to B.CrtYd layer. * PCB: Change a Tg reference I missed. * PCB: Update footprints for parts with mismatched CAD->tape rotation. Adjust a few layer choice and line thickness bits. * PCB: Got cold feet, switched back to rectangular pads. * PCB: Add Eco layers to be visible and Gerber output. * PCB: Use aux origin for plotting, for tidier coordinates. * PCB: Output Gerber job file, because why not? * Schematic: Correct footprints for two reference-related components. * Schematic: Remove manfuacturer and part number for DNP component. * Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination. * PCB: Update netlist and footprints from schematic. * Netlist: Updated component values, footprints. * PCB: Nudge some components and traces to address DRC clearance violations. * PCB: Allow KiCad to update zone timestamps (again?!). * PCB: Generate *all* Gerber layers. * Schematic, PCB: Update revision to 20181025. * PCB: Adjust fab layer annotations orientation and font size. * PCB: Hide mounting hole reference designators on silk layer. * PCB: Shrink U1, U3 pads to get 0.2mm space between pads. * PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options. * PCB: Revise U1 pad shape, mask, paste, thermal drills. Clearance is improved at corner pads. * PCB: Tweak U3 for better thermal pad/drill/mask/paste design. * PCB: Change solder mask color to blue. * Schematic, PCB: Update revision to 20181029. * PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math. * Update schematic * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Clock Manager: Actually store chosen clock reference Similarly-named local was covering a member and discarding the value. * Clock Manager: Reference type which contains source, frequency. * Setup: Display reference source, frequency in frequency correction screen. * LPC43xx API: Add extern "C" for use from C++. * Use LPC43xx API for SGPIO, GPDMA, I2S initialization. * I2S: Add BASE_AUDIO_CLK management. * Add MOTOCON_PWM clock/reset structure. * Serial: Fix dumb typos. * Serial: Remove extra reference operator. * Serial: Cut-and-paste error in structure type name. * Move SCU structure from PAL to LPC43xx API. It'd be nice if I gave some thought to where code should live before I commit it. * VAA power: Move code to HackRF board file It doesn't belong in PAL. * MAX5 CPLD: Add SAMPLE and EXTEST methods. * Flash image: Change packing scheme to use flash more efficiently. Application is now a single image for both M4 bootstrap and M0. Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash). * Clock Manager: Remove PLL1 power down function. * Move and rename peripherals reset function to board module. * Remove unused peripheral/clock management. * Clock Manager: Extract switch to IRC into separate function. * Clock Manager: More explicit shutdown of clocks, clock generator. * Move initialization to board module. * ChibiOS: Rename "application" board, add "baseband" board. There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup. * Clock Manager: Remove unused crystal enable/disable code. * Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown. * Reset peripherals on app shutdown. Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state). * M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0. This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown. * Audio app: Stop audio PLL on shutdown. * M4 HAL: Make LPC43XX_M4_CLK_SRC optional. This was changing the BASE_M4_CLK when a baseband was run. * LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width. * Application board: hide the peripherals_reset function, as it isn't useful except during hardware init. * Consolidate hardware init code to some degree. ClockManager is super-overloaded and murky in its purpose. Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown. * Migrate some startup code to application board. * Si5351: Use correct methods for reset(). update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown. For similar reasons, use set_clock_control() instead of setting internal state and then using the update function. * GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader. * Change application board.c to .cpp, with required dependent changes * Board: Clean up SCU configuration code/data. * I2S: Add shutdown code and use it. * LPC43xx: Consolidate a bunch of structures that had been scattered all over. ...because I'm an undisciplined coder. * I2S: Fix ordering of branch and base clock disable. Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled. * Controls: Save and expose raw navigation wheel switch state I need to do some work on debouncing and ignoring simultaneous key presses. * Controls: Add debug view for switches state. * Controls: Ignore all key presses until all keys are released. This should address some mechanical quirks of the navigation wheel used on the PortaPack. * Clock Manager: Wait for only the necessary PLL to lock. Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL. TODO: Switching PLLs may be kind of pointless now... * CMake: Pull HackRF project from GitHub and build. * CMake: Remove commented code. * CMake: Clone HackRF via HTTPS, not SSH. * CMake: Extra pause for slow post-DFU firmware boot-up. * CMake: TODO to fix SVF/XSVF file source. * CMake: Ask HackRF hackrf_usb to make DFU binary. * Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion. * Travis-CI: Update build environment to Ubuntu xenial Previously Trusty. * Travis-CI: Incorrectly structured my request for dfu-util package. I'm soooo talented. * ldscript: Mark flash, ram with correct R/W/X flags. * ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash. * Receiver: Hide PPM adjustment if clock source is not HackRF crystal. * Documentation: Update product photos and README. * Documentation: Add TCXO feature to README description. * Application: Rearrange files to match HAVOC directory structure. * Map view in AIS (#213) * Added GeoMapView to AISRecentEntryDetailView * Added autoupdate in AIS map * Revert "Map view in AIS (#213)" This reverts commit262c030224. This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted. * Revert "Upstream merge to make new revision of PortaPack work (#206)" This reverts commit920b98f7c9. This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks. * CPLD: Pull bitstream from HackRF project. * SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN. * CPLD: Don't load HackRF CPLD bitstream into RAM. Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary. * CPLD: Tweak clock generator config to match CPLD timing changes in HackRF. * PinConfig: Drive CPLD pins correctly. * CMake: Use jboone/hackrf master branch, now that CPLD fixes are there. * CMake: Fix HackRF CPLD SVF dependency. Build would break on the first pass, but work if you restarted make. * CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree * CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR. * CMake: Choose a CMP0005 policy to quiet CMake warnings. * Settings: Show active clock reference. Only show PPM adjustment for HackRF source. * Radio Settings: Change reference clock text color. Make consistent color with other un-editable text. TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
1187 lines
27 KiB
Plaintext
1187 lines
27 KiB
Plaintext
EESchema Schematic File Version 4
|
||
LIBS:portapack_h1-cache
|
||
EELAYER 26 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 4 6
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Title "PortaPack H1"
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Date "2018-10-29"
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Rev "20181029"
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Comp "ShareBrained Technology, Inc."
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Comment1 "Copyright © 2014-2018 Jared Boone"
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Comment2 "License: GNU General Public License, version 2"
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Comment3 ""
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Comment4 ""
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||
$EndDescr
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||
Text Label 1300 2600 0 60 ~ 0
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MCU_LCD_RD
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$Comp
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||
L power:GND #PWR044
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||
U 1 1 53A8CD34
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P 3700 4200
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||
F 0 "#PWR044" H 3700 4200 30 0001 C CNN
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||
F 1 "GND" H 3700 4130 30 0001 C CNN
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||
F 2 "" H 3700 4200 60 0000 C CNN
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||
F 3 "" H 3700 4200 60 0000 C CNN
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1 3700 4200
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0 -1 -1 0
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$EndComp
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||
$Comp
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||
L power:GND #PWR045
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||
U 1 1 53A8CD3A
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P 3700 4700
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||
F 0 "#PWR045" H 3700 4700 30 0001 C CNN
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||
F 1 "GND" H 3700 4630 30 0001 C CNN
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||
F 2 "" H 3700 4700 60 0000 C CNN
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||
F 3 "" H 3700 4700 60 0000 C CNN
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||
1 3700 4700
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||
0 -1 -1 0
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||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR046
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||
U 1 1 53A8CD40
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||
P 3700 3200
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||
F 0 "#PWR046" H 3700 3200 30 0001 C CNN
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||
F 1 "GND" H 3700 3130 30 0001 C CNN
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||
F 2 "" H 3700 3200 60 0000 C CNN
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||
F 3 "" H 3700 3200 60 0000 C CNN
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1 3700 3200
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||
0 -1 -1 0
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$EndComp
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||
$Comp
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||
L power:GND #PWR047
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U 1 1 53A8CD46
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P 3700 2800
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||
F 0 "#PWR047" H 3700 2800 30 0001 C CNN
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||
F 1 "GND" H 3700 2730 30 0001 C CNN
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||
F 2 "" H 3700 2800 60 0000 C CNN
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||
F 3 "" H 3700 2800 60 0000 C CNN
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||
1 3700 2800
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||
0 -1 -1 0
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||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR048
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||
U 1 1 53A8CD4C
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||
P 3700 2500
|
||
F 0 "#PWR048" H 3700 2500 30 0001 C CNN
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||
F 1 "GND" H 3700 2430 30 0001 C CNN
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||
F 2 "" H 3700 2500 60 0000 C CNN
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||
F 3 "" H 3700 2500 60 0000 C CNN
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||
1 3700 2500
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||
0 -1 -1 0
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||
$EndComp
|
||
$Comp
|
||
L power:+3V3 #PWR049
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||
U 1 1 53A8CD52
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||
P 1900 2900
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||
F 0 "#PWR049" H 1900 2860 30 0001 C CNN
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||
F 1 "+3V3" H 1900 3010 30 0000 C CNN
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||
F 2 "" H 1900 2900 60 0000 C CNN
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||
F 3 "" H 1900 2900 60 0000 C CNN
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||
1 1900 2900
|
||
0 -1 -1 0
|
||
$EndComp
|
||
$Comp
|
||
L power:+3V3 #PWR050
|
||
U 1 1 53A8CD58
|
||
P 1900 4200
|
||
F 0 "#PWR050" H 1900 4160 30 0001 C CNN
|
||
F 1 "+3V3" H 1900 4310 30 0000 C CNN
|
||
F 2 "" H 1900 4200 60 0000 C CNN
|
||
F 3 "" H 1900 4200 60 0000 C CNN
|
||
1 1900 4200
|
||
0 -1 -1 0
|
||
$EndComp
|
||
$Comp
|
||
L power:+3V3 #PWR051
|
||
U 1 1 53A8CD5E
|
||
P 1900 900
|
||
F 0 "#PWR051" H 1900 860 30 0001 C CNN
|
||
F 1 "+3V3" H 1900 1010 30 0000 C CNN
|
||
F 2 "" H 1900 900 60 0000 C CNN
|
||
F 3 "" H 1900 900 60 0000 C CNN
|
||
1 1900 900
|
||
0 -1 -1 0
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR052
|
||
U 1 1 53A8CD64
|
||
P 1900 1400
|
||
F 0 "#PWR052" H 1900 1400 30 0001 C CNN
|
||
F 1 "GND" H 1900 1330 30 0001 C CNN
|
||
F 2 "" H 1900 1400 60 0000 C CNN
|
||
F 3 "" H 1900 1400 60 0000 C CNN
|
||
1 1900 1400
|
||
0 1 1 0
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR053
|
||
U 1 1 53A8CD6A
|
||
P 1900 1500
|
||
F 0 "#PWR053" H 1900 1500 30 0001 C CNN
|
||
F 1 "GND" H 1900 1430 30 0001 C CNN
|
||
F 2 "" H 1900 1500 60 0000 C CNN
|
||
F 3 "" H 1900 1500 60 0000 C CNN
|
||
1 1900 1500
|
||
0 1 1 0
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR054
|
||
U 1 1 53A8CD70
|
||
P 1900 1700
|
||
F 0 "#PWR054" H 1900 1700 30 0001 C CNN
|
||
F 1 "GND" H 1900 1630 30 0001 C CNN
|
||
F 2 "" H 1900 1700 60 0000 C CNN
|
||
F 3 "" H 1900 1700 60 0000 C CNN
|
||
1 1900 1700
|
||
0 1 1 0
|
||
$EndComp
|
||
NoConn ~ 3600 4800
|
||
NoConn ~ 2000 4800
|
||
NoConn ~ 3600 2700
|
||
NoConn ~ 2000 2700
|
||
NoConn ~ 2000 2800
|
||
Text Label 3700 1000 0 60 ~ 0
|
||
MCU_D1
|
||
Text Label 3700 1100 0 60 ~ 0
|
||
MCU_D3
|
||
Text Label 3700 1200 0 60 ~ 0
|
||
MCU_D5
|
||
Text Label 3700 1300 0 60 ~ 0
|
||
MCU_D7
|
||
Text Label 1300 1300 0 60 ~ 0
|
||
MCU_D6
|
||
Text Label 1300 1200 0 60 ~ 0
|
||
MCU_D4
|
||
Text Label 1300 1100 0 60 ~ 0
|
||
MCU_D2
|
||
Text Label 1300 1000 0 60 ~ 0
|
||
MCU_D0
|
||
NoConn ~ 2000 3600
|
||
NoConn ~ 3600 5000
|
||
NoConn ~ 3600 5100
|
||
NoConn ~ 3600 5200
|
||
NoConn ~ 2000 5200
|
||
Text Label 3700 4600 0 60 ~ 0
|
||
PP_CPLD_TDO
|
||
NoConn ~ 2000 4900
|
||
NoConn ~ 3600 4900
|
||
Text Label 1200 5100 0 60 ~ 0
|
||
H1_CPLD_TDI
|
||
Text Label 3900 3300 0 60 ~ 0
|
||
MCU_IO_STBX
|
||
Text Label 1300 3300 0 60 ~ 0
|
||
MCU_ADDR
|
||
Text Label 1300 3400 0 60 ~ 0
|
||
MCU_LCD_WR
|
||
Text Label 3900 3400 0 60 ~ 0
|
||
MCU_DIR
|
||
Text Label 3700 4500 0 60 ~ 0
|
||
PP_CPLD_TMS
|
||
Text Label 1300 3500 0 60 ~ 0
|
||
P2_8
|
||
Text Label 1200 5000 0 60 ~ 0
|
||
H1_CPLD_TCK
|
||
Text Label 1300 2500 0 60 ~ 0
|
||
RESET#
|
||
NoConn ~ 3600 2900
|
||
NoConn ~ 3600 3000
|
||
$Comp
|
||
L hackrf_expansion:HACKRF_ONE_P20 P20
|
||
U 1 1 53A8CDAE
|
||
P 2800 1300
|
||
F 0 "P20" H 2800 1950 60 0000 C CNN
|
||
F 1 "HACKRF_ONE_P20" H 2800 650 60 0000 C CNN
|
||
F 2 "header:HEADER_11X2_REV_SM_254_AP" H 2800 1300 60 0001 C CNN
|
||
F 3 "https://www.samtec.com/products/tsm-111-01-l-dv-a-p-tr" H 2800 1300 60 0001 C CNN
|
||
F 4 "Samtec" H 2800 1300 60 0001 C CNN "Mfr"
|
||
F 5 "TSM⁃111⁃01⁃L⁃DV⁃A⁃P⁃TR" H 2800 1300 60 0001 C CNN "Part"
|
||
1 2800 1300
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L hackrf_expansion:HACKRF_ONE_P22 P22
|
||
U 1 1 53A8CDB6
|
||
P 2800 3000
|
||
F 0 "P22" H 2800 3750 60 0000 C CNN
|
||
F 1 "HACKRF_ONE_P22" H 2800 2250 60 0000 C CNN
|
||
F 2 "header:HEADER_13X2_REV_SM_254_AP" H 2800 3000 60 0001 C CNN
|
||
F 3 "https://www.samtec.com/products/tsm-113-01-l-dv-a-p-tr" H 2800 3000 60 0001 C CNN
|
||
F 4 "Samtec" H 2800 3000 60 0001 C CNN "Mfr"
|
||
F 5 "TSM⁃113⁃01⁃L⁃DV⁃A⁃P⁃TR" H 2800 3000 60 0001 C CNN "Part"
|
||
1 2800 3000
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L hackrf_expansion:HACKRF_ONE_P28 P28
|
||
U 1 1 53A8CDBE
|
||
P 2800 4700
|
||
F 0 "P28" H 2800 5350 60 0000 C CNN
|
||
F 1 "HACKRF_ONE_P28" H 2800 4050 60 0000 C CNN
|
||
F 2 "header:HEADER_11X2_REV_SM_254_AP" H 2800 4700 60 0001 C CNN
|
||
F 3 "https://www.samtec.com/products/tsm-111-01-l-dv-a-p-tr" H 2800 4700 60 0001 C CNN
|
||
F 4 "Samtec" H 2800 4700 60 0001 C CNN "Mfr"
|
||
F 5 "TSM⁃111⁃01⁃L⁃DV⁃A⁃P⁃TR" H 2800 4700 60 0001 C CNN "Part"
|
||
1 2800 4700
|
||
1 0 0 -1
|
||
$EndComp
|
||
NoConn ~ 3600 800
|
||
NoConn ~ 3600 900
|
||
Wire Wire Line
|
||
1100 5000 2000 5000
|
||
Wire Wire Line
|
||
4400 4500 3600 4500
|
||
Wire Wire Line
|
||
1200 3500 2000 3500
|
||
Wire Wire Line
|
||
1200 3400 2000 3400
|
||
Wire Wire Line
|
||
4600 3400 3600 3400
|
||
Wire Wire Line
|
||
1200 3300 2000 3300
|
||
Wire Wire Line
|
||
4600 3300 3600 3300
|
||
Wire Wire Line
|
||
1100 5100 1900 5100
|
||
Wire Wire Line
|
||
3700 3600 3600 3600
|
||
Wire Wire Line
|
||
3700 3500 3600 3500
|
||
Wire Wire Line
|
||
1700 800 2000 800
|
||
Wire Wire Line
|
||
3600 3100 3800 3100
|
||
Wire Wire Line
|
||
1200 3200 2000 3200
|
||
Wire Wire Line
|
||
1200 3100 2000 3100
|
||
Wire Wire Line
|
||
1200 3000 2000 3000
|
||
Wire Wire Line
|
||
1700 4300 2000 4300
|
||
Wire Wire Line
|
||
1700 4400 2000 4400
|
||
Wire Wire Line
|
||
1700 4500 2000 4500
|
||
Wire Wire Line
|
||
1700 4700 2000 4700
|
||
Wire Wire Line
|
||
1700 4600 2000 4600
|
||
Wire Wire Line
|
||
4400 4600 3600 4600
|
||
Wire Wire Line
|
||
4400 4400 3600 4400
|
||
Wire Wire Line
|
||
4400 4300 3600 4300
|
||
Wire Wire Line
|
||
2000 2500 1200 2500
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L altera:5M40ZE64 U3
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|
||
L power:+3V3 #PWR055
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$Comp
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$Comp
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$Comp
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L power:+1V8 #PWR058
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$Comp
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$Comp
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L power:+1V8 #PWR060
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$Comp
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L power:+1V8 #PWR061
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$Comp
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L power:+3V3 #PWR062
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U 1 1 53A8D521
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$Comp
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L Device:C C28
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$Comp
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L power:GND #PWR063
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$Comp
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L Device:C C30
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$Comp
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L Device:C C29
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$Comp
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L Device:C C31
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$Comp
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L power:GND #PWR064
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$Comp
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L power:GND #PWR065
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$EndComp
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$Comp
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L power:GND #PWR066
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$EndComp
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$Comp
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L power:GND #PWR067
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$EndComp
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$Comp
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L Device:C C33
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$EndComp
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$Comp
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L Device:C C35
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$Comp
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L power:GND #PWR068
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$Comp
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L power:+1V8 #PWR069
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$Comp
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L Device:C C32
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$EndComp
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$Comp
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L Device:C C34
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$EndComp
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$Comp
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L power:GND #PWR070
|
||
U 1 1 53A8D5CE
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$EndComp
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$Comp
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L power:GND #PWR071
|
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U 1 1 53A8D5D4
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1 5700 6400
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$EndComp
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$Comp
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||
L Device:C C36
|
||
U 1 1 53A8D5DA
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|
||
F 3 "" H 6100 7100 60 0000 C CNN
|
||
F 4 "Murata" H 6100 7100 60 0001 C CNN "Mfr"
|
||
F 5 "GRM21BR61A106KE19" H 6100 7100 60 0001 C CNN "Part"
|
||
1 6100 7100
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L Device:C C37
|
||
U 1 1 53A8D5E0
|
||
P 6500 7100
|
||
F 0 "C37" H 6550 7200 50 0000 L CNN
|
||
F 1 "10U" H 6550 7000 50 0000 L CNN
|
||
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6500 7100 60 0001 C CNN
|
||
F 3 "" H 6500 7100 60 0000 C CNN
|
||
F 4 "Murata" H 6500 7100 60 0001 C CNN "Mfr"
|
||
F 5 "GRM21BR61A106KE19" H 6500 7100 60 0001 C CNN "Part"
|
||
1 6500 7100
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR072
|
||
U 1 1 53A8D5E6
|
||
P 6500 7400
|
||
F 0 "#PWR072" H 6500 7400 30 0001 C CNN
|
||
F 1 "GND" H 6500 7330 30 0001 C CNN
|
||
F 2 "" H 6500 7400 60 0000 C CNN
|
||
F 3 "" H 6500 7400 60 0000 C CNN
|
||
1 6500 7400
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR073
|
||
U 1 1 53A8D5EC
|
||
P 6100 7400
|
||
F 0 "#PWR073" H 6100 7400 30 0001 C CNN
|
||
F 1 "GND" H 6100 7330 30 0001 C CNN
|
||
F 2 "" H 6100 7400 60 0000 C CNN
|
||
F 3 "" H 6100 7400 60 0000 C CNN
|
||
1 6100 7400
|
||
1 0 0 -1
|
||
$EndComp
|
||
Connection ~ 6100 6800
|
||
Connection ~ 5700 6800
|
||
Connection ~ 5300 5800
|
||
Connection ~ 4900 5800
|
||
Connection ~ 5300 6800
|
||
Connection ~ 4900 6800
|
||
Connection ~ 4500 6800
|
||
Wire Wire Line
|
||
4500 6800 4900 6800
|
||
Wire Wire Line
|
||
4500 6700 4500 6800
|
||
Connection ~ 4500 5800
|
||
Wire Wire Line
|
||
4500 5800 4900 5800
|
||
Wire Wire Line
|
||
4500 5700 4500 5800
|
||
Wire Wire Line
|
||
9100 5500 9100 4650
|
||
Text Label 3900 2600 0 60 ~ 0
|
||
MCU_LCD_TE
|
||
Text Label 9100 5400 1 60 ~ 0
|
||
MCU_LCD_TE
|
||
Text Label 10350 2900 0 60 ~ 0
|
||
MCU_DIR
|
||
Text Label 10350 3100 0 60 ~ 0
|
||
MCU_LCD_WR
|
||
Text Label 7800 5400 1 60 ~ 0
|
||
MCU_D7
|
||
Text Label 7900 5400 1 60 ~ 0
|
||
MCU_D6
|
||
Text Label 8000 5400 1 60 ~ 0
|
||
MCU_D4
|
||
Text Label 8100 5400 1 60 ~ 0
|
||
MCU_D5
|
||
Text Label 8200 5400 1 60 ~ 0
|
||
MCU_D3
|
||
Text Label 8400 5400 1 60 ~ 0
|
||
MCU_D2
|
||
Text Label 8600 5400 1 60 ~ 0
|
||
MCU_D0
|
||
Text Label 8700 5400 1 60 ~ 0
|
||
MCU_D1
|
||
Wire Wire Line
|
||
1900 5100 1900 5300
|
||
Wire Wire Line
|
||
1900 5300 1800 5300
|
||
Connection ~ 1900 5100
|
||
Entry Wire Line
|
||
8200 650 8300 750
|
||
Entry Wire Line
|
||
8400 650 8500 750
|
||
Entry Wire Line
|
||
8500 650 8600 750
|
||
Entry Wire Line
|
||
8600 650 8700 750
|
||
Entry Wire Line
|
||
8700 650 8800 750
|
||
Entry Wire Line
|
||
8800 650 8900 750
|
||
Entry Wire Line
|
||
8900 650 9000 750
|
||
Entry Wire Line
|
||
9000 650 9100 750
|
||
Entry Wire Line
|
||
9100 650 9200 750
|
||
Entry Wire Line
|
||
10650 2700 10750 2600
|
||
Entry Wire Line
|
||
10650 2800 10750 2700
|
||
Wire Wire Line
|
||
7700 1450 7700 1350
|
||
Wire Wire Line
|
||
7700 1350 7600 1350
|
||
Wire Wire Line
|
||
7600 1150 7800 1150
|
||
Wire Wire Line
|
||
7800 1150 7800 1450
|
||
Text HLabel 7600 650 0 60 BiDi ~ 0
|
||
LCD_DB[15..0]
|
||
Text HLabel 7600 1150 0 60 Input ~ 0
|
||
LCD_TE
|
||
Text HLabel 6100 3100 0 60 Input ~ 0
|
||
SW_R
|
||
Text HLabel 6100 3400 0 60 Input ~ 0
|
||
SW_ROT_B
|
||
Text HLabel 6100 3300 0 60 Input ~ 0
|
||
SW_ROT_A
|
||
Text HLabel 6100 3200 0 60 Input ~ 0
|
||
SW_D
|
||
Text HLabel 6100 3500 0 60 Input ~ 0
|
||
SW_SEL
|
||
Text HLabel 8500 5500 3 60 Input ~ 0
|
||
SW_U
|
||
Text HLabel 8800 5500 3 60 Input ~ 0
|
||
SW_L
|
||
Text HLabel 10300 3400 2 60 Output ~ 0
|
||
LCD_BACKLIGHT
|
||
Text HLabel 10300 3300 2 60 Output ~ 0
|
||
LCD_RESET#
|
||
Text HLabel 7600 950 0 60 Output ~ 0
|
||
LCD_RS
|
||
Text HLabel 7600 750 0 60 Output ~ 0
|
||
LCD_RD#
|
||
Text HLabel 7600 850 0 60 Output ~ 0
|
||
LCD_WR#
|
||
Text HLabel 3700 1700 2 60 BiDi ~ 0
|
||
TP_U
|
||
Text HLabel 3700 1600 2 60 BiDi ~ 0
|
||
TP_L
|
||
Text HLabel 3700 1500 2 60 BiDi ~ 0
|
||
TP_D
|
||
Text HLabel 3700 1400 2 60 BiDi ~ 0
|
||
TP_R
|
||
Text HLabel 7600 1350 0 60 BiDi ~ 0
|
||
TP_R
|
||
Text HLabel 6100 2300 0 60 BiDi ~ 0
|
||
TP_D
|
||
Text HLabel 6100 2400 0 60 BiDi ~ 0
|
||
TP_L
|
||
Text HLabel 6100 2500 0 60 BiDi ~ 0
|
||
TP_U
|
||
Text HLabel 1200 3000 0 60 Output ~ 0
|
||
I2S0_TX_SDA
|
||
Text HLabel 1200 3100 0 60 BiDi ~ 0
|
||
I2S0_WS
|
||
Text HLabel 1200 3200 0 60 Output ~ 0
|
||
I2S0_MCLK
|
||
Text HLabel 3800 3100 2 60 BiDi ~ 0
|
||
I2S0_SCK
|
||
Text HLabel 3700 3500 2 60 BiDi ~ 0
|
||
SDA
|
||
Text HLabel 3700 3600 2 60 Output ~ 0
|
||
SCL
|
||
Text HLabel 1700 4300 0 60 Input ~ 0
|
||
SD_CD
|
||
Text HLabel 1700 4400 0 60 BiDi ~ 0
|
||
SD_DAT2
|
||
Text HLabel 1700 4500 0 60 BiDi ~ 0
|
||
SD_DAT0
|
||
Text HLabel 1700 4600 0 60 BiDi ~ 0
|
||
SD_CMD
|
||
Text HLabel 1700 4700 0 60 Output ~ 0
|
||
SD_CLK
|
||
Text HLabel 4400 4300 2 60 BiDi ~ 0
|
||
SD_DAT3
|
||
Text HLabel 4400 4400 2 60 BiDi ~ 0
|
||
SD_DAT1
|
||
Text HLabel 1800 5300 0 60 Input ~ 0
|
||
I2S0_RX_SDA
|
||
Text Label 10150 3700 0 60 ~ 0
|
||
P2_8
|
||
Wire Wire Line
|
||
10050 3300 10300 3300
|
||
Wire Wire Line
|
||
10300 3400 10050 3400
|
||
$Comp
|
||
L Device:C C42
|
||
U 1 1 53B1911F
|
||
P 6100 6100
|
||
F 0 "C42" H 6150 6200 50 0000 L CNN
|
||
F 1 "10U" H 6150 6000 50 0000 L CNN
|
||
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6100 6100 60 0001 C CNN
|
||
F 3 "" H 6100 6100 60 0000 C CNN
|
||
F 4 "Murata" H 6100 6100 60 0001 C CNN "Mfr"
|
||
F 5 "GRM21BR61A106KE19" H 6100 6100 60 0001 C CNN "Part"
|
||
1 6100 6100
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR074
|
||
U 1 1 53B1912C
|
||
P 6100 6400
|
||
F 0 "#PWR074" H 6100 6400 30 0001 C CNN
|
||
F 1 "GND" H 6100 6330 30 0001 C CNN
|
||
F 2 "" H 6100 6400 60 0000 C CNN
|
||
F 3 "" H 6100 6400 60 0000 C CNN
|
||
1 6100 6400
|
||
1 0 0 -1
|
||
$EndComp
|
||
Connection ~ 5700 5800
|
||
$Comp
|
||
L Device:C C43
|
||
U 1 1 53B1A065
|
||
P 6500 6100
|
||
F 0 "C43" H 6550 6200 50 0000 L CNN
|
||
F 1 "10U" H 6550 6000 50 0000 L CNN
|
||
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 6500 6100 60 0001 C CNN
|
||
F 3 "" H 6500 6100 60 0000 C CNN
|
||
F 4 "Murata" H 6500 6100 60 0001 C CNN "Mfr"
|
||
F 5 "GRM21BR61A106KE19" H 6500 6100 60 0001 C CNN "Part"
|
||
1 6500 6100
|
||
1 0 0 -1
|
||
$EndComp
|
||
$Comp
|
||
L power:GND #PWR075
|
||
U 1 1 53B1A072
|
||
P 6500 6400
|
||
F 0 "#PWR075" H 6500 6400 30 0001 C CNN
|
||
F 1 "GND" H 6500 6330 30 0001 C CNN
|
||
F 2 "" H 6500 6400 60 0000 C CNN
|
||
F 3 "" H 6500 6400 60 0000 C CNN
|
||
1 6500 6400
|
||
1 0 0 -1
|
||
$EndComp
|
||
Connection ~ 6100 5800
|
||
Wire Wire Line
|
||
6850 2600 6100 2600
|
||
Wire Wire Line
|
||
10700 3800 10050 3800
|
||
Text HLabel 7600 1050 0 60 Output ~ 0
|
||
LCD_CS#
|
||
Wire Wire Line
|
||
3700 1800 3600 1800
|
||
Wire Wire Line
|
||
1700 1800 2000 1800
|
||
Wire Wire Line
|
||
1700 1600 2000 1600
|
||
Wire Wire Line
|
||
10650 2600 10050 2600
|
||
Wire Wire Line
|
||
10650 2500 10050 2500
|
||
Wire Wire Line
|
||
10650 2400 10050 2400
|
||
Entry Wire Line
|
||
10650 2400 10750 2300
|
||
Entry Wire Line
|
||
10650 2500 10750 2400
|
||
Entry Wire Line
|
||
10650 2600 10750 2500
|
||
Wire Wire Line
|
||
7600 950 7900 950
|
||
Wire Wire Line
|
||
7900 950 7900 1450
|
||
Wire Wire Line
|
||
7600 850 8000 850
|
||
Wire Wire Line
|
||
8000 850 8000 1450
|
||
Wire Wire Line
|
||
7600 750 8100 750
|
||
Wire Wire Line
|
||
8100 750 8100 1450
|
||
Wire Wire Line
|
||
10650 2300 10050 2300
|
||
Entry Wire Line
|
||
10650 2300 10750 2200
|
||
Wire Wire Line
|
||
7600 1050 7800 1050
|
||
Text HLabel 6100 2600 0 60 Output ~ 0
|
||
AUDIO_RESET#
|
||
Text HLabel 3700 1800 2 60 Input ~ 0
|
||
VIN
|
||
Text HLabel 1700 1800 0 60 Output ~ 0
|
||
VBUS
|
||
Text HLabel 1700 1600 0 60 Input ~ 0
|
||
VBUSCTRL
|
||
Text HLabel 1700 800 0 60 Input ~ 0
|
||
VBAT
|
||
Text Notes 4500 1900 0 60 ~ 0
|
||
Init: I/O is hi-Z with pull-ups.\nSRAM download when VCCINT reaches 1V55.\nUser mode once downloaded and VCCIO OK.\nVCCINT stable to user mode: 200 usec max.\nVCCIOs stable to user mode: 2 usec.\n\nPull-ups: 5-25k @ 3V3, 25-60k @ 1V8.\nExternal R-pull: 1K PD, 10K PU recommended.\nVCCIO=3V3: 2V5, 3V3 inputs OK.\nVCCIO=1V8: 1V5, 1V8, 2V5, 3V3 inputs OK.\n\nJTAG active w/VCCINT, but refers to VCCIO.\nTDI, TMS: weak internal PU\nTCK: weak internal PD (keep low at power-up)
|
||
Wire Wire Line
|
||
10700 3700 10050 3700
|
||
Entry Wire Line
|
||
8100 650 8200 750
|
||
Wire Wire Line
|
||
8200 1450 8200 750
|
||
Wire Wire Line
|
||
11050 2900 10050 2900
|
||
Wire Wire Line
|
||
11050 3100 10050 3100
|
||
$Comp
|
||
L power:GND #PWR076
|
||
U 1 1 58FC4CC1
|
||
P 7800 1050
|
||
F 0 "#PWR076" H 7800 1050 30 0001 C CNN
|
||
F 1 "GND" H 7800 980 30 0001 C CNN
|
||
F 2 "" H 7800 1050 60 0000 C CNN
|
||
F 3 "" H 7800 1050 60 0000 C CNN
|
||
1 7800 1050
|
||
0 -1 -1 0
|
||
$EndComp
|
||
Wire Wire Line
|
||
6100 6800 6500 6800
|
||
Wire Wire Line
|
||
5700 6800 6100 6800
|
||
Wire Wire Line
|
||
5300 5800 5700 5800
|
||
Wire Wire Line
|
||
4900 5800 5300 5800
|
||
Wire Wire Line
|
||
5300 6800 5700 6800
|
||
Wire Wire Line
|
||
4900 6800 5300 6800
|
||
Wire Wire Line
|
||
1900 5100 2000 5100
|
||
Wire Wire Line
|
||
5700 5800 6100 5800
|
||
Wire Wire Line
|
||
6100 5800 6500 5800
|
||
Wire Wire Line
|
||
4500 5800 4500 5950
|
||
Wire Wire Line
|
||
4500 6250 4500 6400
|
||
Wire Wire Line
|
||
4900 6250 4900 6400
|
||
Wire Wire Line
|
||
4900 5800 4900 5950
|
||
Wire Wire Line
|
||
5300 5800 5300 5950
|
||
Wire Wire Line
|
||
5300 6250 5300 6400
|
||
Wire Wire Line
|
||
5700 6250 5700 6400
|
||
Wire Wire Line
|
||
5700 5800 5700 5950
|
||
Wire Wire Line
|
||
6100 5800 6100 5950
|
||
Wire Wire Line
|
||
6100 6250 6100 6400
|
||
Wire Wire Line
|
||
6500 6250 6500 6400
|
||
Wire Wire Line
|
||
6500 5800 6500 5950
|
||
Wire Wire Line
|
||
4500 6800 4500 6950
|
||
Wire Wire Line
|
||
4500 7250 4500 7400
|
||
Wire Wire Line
|
||
4900 7250 4900 7400
|
||
Wire Wire Line
|
||
4900 6800 4900 6950
|
||
Wire Wire Line
|
||
5300 6800 5300 6950
|
||
Wire Wire Line
|
||
5300 7250 5300 7400
|
||
Wire Wire Line
|
||
5700 7250 5700 7400
|
||
Wire Wire Line
|
||
5700 6800 5700 6950
|
||
Wire Wire Line
|
||
6100 6800 6100 6950
|
||
Wire Wire Line
|
||
6100 7250 6100 7400
|
||
Wire Wire Line
|
||
6500 7250 6500 7400
|
||
Wire Wire Line
|
||
6500 6800 6500 6950
|
||
Wire Wire Line
|
||
3800 2400 3600 2400
|
||
Text HLabel 3800 2400 2 60 BiDi ~ 0
|
||
CLKIN
|
||
Text HLabel 6100 2700 0 60 Output ~ 0
|
||
REF_EN
|
||
Wire Wire Line
|
||
6100 2700 6850 2700
|
||
NoConn ~ 2000 2400
|
||
Text HLabel 10300 3500 2 60 Input ~ 0
|
||
GPS_TX_READY
|
||
Wire Wire Line
|
||
10300 3500 10050 3500
|
||
Text HLabel 10300 3600 2 60 Input ~ 0
|
||
GPS_TIMEPULSE
|
||
Wire Wire Line
|
||
10050 3600 10300 3600
|
||
Text HLabel 6100 2900 0 60 Output ~ 0
|
||
GPS_RESET#
|
||
Wire Wire Line
|
||
6100 2900 6850 2900
|
||
Wire Bus Line
|
||
10750 650 10750 2700
|
||
Wire Bus Line
|
||
7600 650 10750 650
|
||
$EndSCHEMATC
|