8 Commits

Author	SHA1	Message	Date
Jared Boone	a03a72474d	Insert IDIVC into audio MCLK path, so it can be divided.	2016-01-29 15:17:05 -08:00
Jared Boone	f1ca3fe5bb	Switch RFFC5072, MAX2837 back to 40MHz reference. ... Turns out the MAX2837 can't tune the necessary range when given a 50MHz reference. Oops.	2015-09-02 17:45:19 -07:00
Jared Boone	4974774f82	Simplify PLL math when correcting for PPM.	2015-08-25 17:56:03 -07:00
Jared Boone	fe7dcdc613	Function to adjust clock generator XTAL PLL frequency. ... Needed to switch PLLA to operate in fractional mode.	2015-08-24 12:09:11 -07:00
Jared Boone	8797aa9758	Stop audio PLL if shutting down GP_CLKIN clock source.	2015-08-01 13:45:52 -07:00
Jared Boone	bfc73a6675	Move update_peripheral_clocks ... Incorrect order of operations would hang execution if switching to IRC.	2015-08-01 13:44:52 -07:00
Jared Boone	c025a2bba2	Code to shut down ClockManager-controlled devices.	2015-08-01 13:43:58 -07:00
Jared Boone	dc6fee8370	Initial firmware commit.	2015-07-08 08:39:24 -07:00