Jared Boone
d3acd79df8
Add PCB stack data and diagram.
2015-08-30 16:23:55 -07:00
Jared Boone
375cf6f238
Tighten solder mask around LCD connector.
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Shooting for 4mil mask web between pads.
2015-08-30 14:35:04 -07:00
Jared Boone
84b92365f9
Move and shrink copper layer legend.
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Doesn't need to be visible after assembly. I think.
2015-08-30 10:14:36 -07:00
Jared Boone
ea2cfb7ad2
Center text in layer legend.
2015-08-30 09:42:47 -07:00
Jared Boone
732561d01c
Change vias to 13mil, 7mil annular ring.
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Was 13.5mm, but why?!?
2015-08-29 22:31:29 -07:00
Jared Boone
1340991dba
Reduce solder mask margin on WM8731.
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Trying to squeeze some mask web in there!
2015-08-29 18:14:23 -07:00
Jared Boone
56c7c31cbb
More footprint units cleanup.
2015-08-29 17:54:26 -07:00
Jared Boone
bda376df4b
KiCad added courtyard layers.
2015-08-29 17:20:41 -07:00
Jared Boone
436e6fd21b
Footprint cleanup
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Remove courtyard lines from silkscreen.
Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units).
Restore U3 refdes silkscreen visibility.
2015-08-29 17:14:06 -07:00
Jared Boone
c78b7fe196
Reduce mask margin on QFP pads.
2015-08-29 16:12:45 -07:00
Jared Boone
d61f3802cb
Remove line in/out components and traces, microphone.
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Clean up traces and via stitching affected by removed components.
2015-08-27 16:54:38 -07:00
Jared Boone
29243a5fd1
Schematic and netlist from schematic modifications.
2015-08-27 16:54:38 -07:00
Jared Boone
70d7ecc51b
Clean up PCB net labels to match code, CPLD.
2015-08-27 16:54:38 -07:00
Jared Boone
75d9aa9c73
Remove extra CPLD code internal signals.
2015-08-27 16:54:38 -07:00
Jared Boone
19764ce693
Swap function of P2_8, P2_4 in schematic, firmware, CPLD.
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gpio_unused: P2_4 -> P2_8
gpio_lcd_rd: P2_8 -> P2_4
P2_8 is a very long line, shared with DFU button.
Revise schematic to match CPLD signal names.
2015-08-27 16:54:38 -07:00
Jared Boone
b6e25692dc
Label 1V8 regulator bypass/adjust capacitor as DNI.
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Was already DNI in assembly BOM. TCR2EF shows that pin as NC.
2015-08-27 16:54:38 -07:00
Jared Boone
1ca4f45d9e
Change VBAT capacitor to DNI.
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HackRF One has 100nF capacitor on VBAT. Having 10uF capacitor on PortaPack VBAT may slowly drain the coin cell when in storage, and add a bit of leakage current when installed.
2015-08-27 16:54:38 -07:00
Jared Boone
8dfd68a6b3
Removed electret microphone.
2015-08-27 16:54:37 -07:00
Jared Boone
cd4840f1f9
Remove line in/out circuitry.
2015-08-27 16:54:37 -07:00
Jared Boone
84ffaaef33
Back-annotate CVPCB data into schematic.
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Remove CVPCB .cmp file, since it's a deprecated by the KiCad project.
2015-08-27 16:54:37 -07:00
Jared Boone
bf4521bf35
Update schematic issue/copyright date.
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KiCad also made some automatic tweaks for latest build (bzr 6109).
2015-08-27 16:54:37 -07:00
Jared Boone
fcec6d6100
OpenSCAD version of case.
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Minor changes were made between this version and the final version. This earlier version is available via Shapeways, at https://www.shapeways.com/product/EGG3EWPAY/portapack-h1-case-round-20150410-0945
Addresses issue #30 .
2015-08-01 22:27:08 -07:00
Jared Boone
565ea41e92
Hardware gitignore
2015-07-16 10:01:19 -07:00
Jared Boone
604389f8cd
Initial release of schematic, PCB, CPLD code.
2015-07-16 09:54:15 -07:00
